linux/drivers/gpu/drm/i915/intel_pcode.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2013-2021 Intel Corporation
 */

#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_pcode.h"

static int gen6_check_mailbox_status(u32 mbox)
{ … }

static int gen7_check_mailbox_status(u32 mbox)
{ … }

static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
			  u32 *val, u32 *val1,
			  int fast_timeout_us, int slow_timeout_ms,
			  bool is_read)
{ … }

int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
{ … }

int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
			    int fast_timeout_us, int slow_timeout_ms)
{ … }

static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
				  u32 request, u32 reply_mask, u32 reply,
				  u32 *status)
{ … }

/**
 * skl_pcode_request - send PCODE request until acknowledgment
 * @uncore: uncore
 * @mbox: PCODE mailbox ID the request is targeted for
 * @request: request ID
 * @reply_mask: mask used to check for request acknowledgment
 * @reply: value used to check for request acknowledgment
 * @timeout_base_ms: timeout for polling with preemption enabled
 *
 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
 * The request is acknowledged once the PCODE reply dword equals @reply after
 * applying @reply_mask. Polling is first attempted with preemption enabled
 * for @timeout_base_ms and if this times out for another 50 ms with
 * preemption disabled.
 *
 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
 * other error as reported by PCODE.
 */
int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms)
{ … }

static int pcode_init_wait(struct intel_uncore *uncore, int timeout_ms)
{ … }

int intel_pcode_init(struct intel_uncore *uncore)
{ … }

int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
{ … }

int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
{ … }