/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_MCHBAR_REGS__ #define __INTEL_MCHBAR_REGS__ #include "i915_reg_defs.h" /* * MCHBAR mirror. * * This mirrors the MCHBAR MMIO space whose location is determined by * device 0 function 0's pci config register 0x44 or 0x48 and matches it in * every way. It is not accessible from the CP register read instructions. * * Starting from Haswell, you can't write registers using the MCHBAR mirror, * just read. */ #define MCHBAR_MIRROR_BASE … #define MCHBAR_MIRROR_BASE_SNB … #define CTG_STOLEN_RESERVED … #define ELK_STOLEN_RESERVED … #define G4X_STOLEN_RESERVED_ADDR1_MASK … #define G4X_STOLEN_RESERVED_ADDR2_MASK … #define G4X_STOLEN_RESERVED_ENABLE … /* Pineview MCH register contains DDR3 setting */ #define CSHRDDR3CTL … #define CSHRDDR3CTL_DDR3 … /* 915-945 and GM965 MCH register controlling DRAM channel access */ #define DCC … #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL … #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC … #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED … #define DCC_ADDRESSING_MODE_MASK … #define DCC_CHANNEL_XOR_DISABLE … #define DCC_CHANNEL_XOR_BIT_17 … #define DCC2 … #define DCC2_MODIFIED_ENHANCED_DISABLE … /* 965 MCH register controlling DRAM channel configuration */ #define C0DRB3_BW … #define C1DRB3_BW … /* Clocking configuration register */ #define CLKCFG … #define CLKCFG_FSB_400 … #define CLKCFG_FSB_400_ALT … #define CLKCFG_FSB_533 … #define CLKCFG_FSB_667 … #define CLKCFG_FSB_800 … #define CLKCFG_FSB_1067 … #define CLKCFG_FSB_1067_ALT … #define CLKCFG_FSB_1333 … #define CLKCFG_FSB_1333_ALT … #define CLKCFG_FSB_1600_ALT … #define CLKCFG_FSB_MASK … #define CLKCFG_MEM_533 … #define CLKCFG_MEM_667 … #define CLKCFG_MEM_800 … #define CLKCFG_MEM_MASK … #define HPLLVCO_MOBILE … #define HPLLVCO … #define TSC1 … #define TSE … #define TR1 … #define TSFS … #define TSFS_SLOPE_MASK … #define TSFS_SLOPE_SHIFT … #define TSFS_INTR_MASK … /* Memory latency timer register */ #define MLTR_ILK … /* the unit of memory self-refresh latency time is 0.5us */ #define MLTR_WM2_MASK … #define MLTR_WM1_MASK … #define CSIPLL0 … #define DDRMPLL1 … #define ILK_GDSR … #define ILK_GRDOM_FULL … #define ILK_GRDOM_RENDER … #define ILK_GRDOM_MEDIA … #define ILK_GRDOM_MASK … #define ILK_GRDOM_RESET_ENABLE … #define BXT_D_CR_DRP0_DUNIT8 … #define BXT_D_CR_DRP0_DUNIT9 … #define BXT_D_CR_DRP0_DUNIT_START … #define BXT_D_CR_DRP0_DUNIT_END … #define BXT_D_CR_DRP0_DUNIT(x) … #define BXT_DRAM_RANK_MASK … #define BXT_DRAM_RANK_SINGLE … #define BXT_DRAM_RANK_DUAL … #define BXT_DRAM_WIDTH_MASK … #define BXT_DRAM_WIDTH_SHIFT … #define BXT_DRAM_WIDTH_X8 … #define BXT_DRAM_WIDTH_X16 … #define BXT_DRAM_WIDTH_X32 … #define BXT_DRAM_WIDTH_X64 … #define BXT_DRAM_SIZE_MASK … #define BXT_DRAM_SIZE_SHIFT … #define BXT_DRAM_SIZE_4GBIT … #define BXT_DRAM_SIZE_6GBIT … #define BXT_DRAM_SIZE_8GBIT … #define BXT_DRAM_SIZE_12GBIT … #define BXT_DRAM_SIZE_16GBIT … #define BXT_DRAM_TYPE_MASK … #define BXT_DRAM_TYPE_SHIFT … #define BXT_DRAM_TYPE_DDR3 … #define BXT_DRAM_TYPE_LPDDR3 … #define BXT_DRAM_TYPE_LPDDR4 … #define BXT_DRAM_TYPE_DDR4 … #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR … #define DG1_DRAM_T_RDPRE_MASK … #define DG1_DRAM_T_RP_MASK … #define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH … #define DG1_DRAM_T_RCD_MASK … #define DG1_DRAM_T_RAS_MASK … #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN … #define SKL_DRAM_DDR_TYPE_MASK … #define SKL_DRAM_DDR_TYPE_DDR4 … #define SKL_DRAM_DDR_TYPE_DDR3 … #define SKL_DRAM_DDR_TYPE_LPDDR3 … #define SKL_DRAM_DDR_TYPE_LPDDR4 … /* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 … #define MAD_DIMM_C1 … #define MAD_DIMM_C2 … #define MAD_DIMM_ECC_MASK … #define MAD_DIMM_ECC_OFF … #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF … #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON … #define MAD_DIMM_ECC_ON … #define MAD_DIMM_ENH_INTERLEAVE … #define MAD_DIMM_RANK_INTERLEAVE … #define MAD_DIMM_B_WIDTH_X16 … #define MAD_DIMM_A_WIDTH_X16 … #define MAD_DIMM_B_DUAL_RANK … #define MAD_DIMM_A_DUAL_RANK … #define MAD_DIMM_A_SELECT … /* DIMM sizes are in multiples of 256mb. */ #define MAD_DIMM_B_SIZE_SHIFT … #define MAD_DIMM_B_SIZE_MASK … #define MAD_DIMM_A_SIZE_SHIFT … #define MAD_DIMM_A_SIZE_MASK … #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN … #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN … #define SKL_DRAM_S_SHIFT … #define SKL_DRAM_SIZE_MASK … #define SKL_DRAM_WIDTH_MASK … #define SKL_DRAM_WIDTH_SHIFT … #define SKL_DRAM_WIDTH_X8 … #define SKL_DRAM_WIDTH_X16 … #define SKL_DRAM_WIDTH_X32 … #define SKL_DRAM_RANK_MASK … #define SKL_DRAM_RANK_SHIFT … #define SKL_DRAM_RANK_1 … #define SKL_DRAM_RANK_2 … #define SKL_DRAM_RANK_MASK … #define ICL_DRAM_SIZE_MASK … #define ICL_DRAM_WIDTH_MASK … #define ICL_DRAM_WIDTH_SHIFT … #define ICL_DRAM_WIDTH_X8 … #define ICL_DRAM_WIDTH_X16 … #define ICL_DRAM_WIDTH_X32 … #define ICL_DRAM_RANK_MASK … #define ICL_DRAM_RANK_SHIFT … #define ICL_DRAM_RANK_1 … #define ICL_DRAM_RANK_2 … #define ICL_DRAM_RANK_3 … #define ICL_DRAM_RANK_4 … #define SA_PERF_STATUS_0_0_0_MCHBAR_PC … #define DG1_QCLK_RATIO_MASK … #define DG1_QCLK_REFERENCE … /* * *_PACKAGE_POWER_SKU - SKU power and timing parameters. */ #define PCU_PACKAGE_POWER_SKU … #define PKG_PKG_TDP … #define PKG_MIN_PWR … #define PKG_MAX_PWR … #define PKG_MAX_WIN … #define PKG_MAX_WIN_X … #define PKG_MAX_WIN_Y … #define PCU_PACKAGE_POWER_SKU_UNIT … #define PKG_PWR_UNIT … #define PKG_ENERGY_UNIT … #define PKG_TIME_UNIT … #define PCU_PACKAGE_ENERGY_STATUS … #define GEN6_GT_PERF_STATUS … #define GEN6_RP_STATE_LIMITS … #define GEN6_RP_STATE_CAP … #define RP0_CAP_MASK … #define RP1_CAP_MASK … #define RPN_CAP_MASK … #define GEN10_FREQ_INFO_REC … #define RPE_MASK … #define PCU_PACKAGE_RAPL_LIMIT … #define PKG_PWR_LIM_1 … #define PKG_PWR_LIM_1_EN … #define PKG_PWR_LIM_1_TIME … #define PKG_PWR_LIM_1_TIME_X … #define PKG_PWR_LIM_1_TIME_Y … /* snb MCH registers for priority tuning */ #define MCH_SSKPD … #define SSKPD_NEW_WM0_MASK_HSW … #define SSKPD_WM4_MASK_HSW … #define SSKPD_WM3_MASK_HSW … #define SSKPD_WM2_MASK_HSW … #define SSKPD_WM1_MASK_HSW … #define SSKPD_OLD_WM0_MASK_HSW … #define SSKPD_WM3_MASK_SNB … #define SSKPD_WM2_MASK_SNB … #define SSKPD_WM1_MASK_SNB … #define SSKPD_WM0_MASK_SNB … /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ #define DCLK … #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU … #define DG1_GEAR_TYPE … /* * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using intel_uncore_write. */ #define D_COMP_HSW … #define D_COMP_RCOMP_IN_PROGRESS … #define D_COMP_COMP_FORCE … #define D_COMP_COMP_DISABLE … #define BXT_GT_PERF_STATUS … #endif /* __INTEL_MCHBAR_REGS */
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