/* SPDX-License-Identifier: MIT*/ /* * Copyright © 2003-2018 Intel Corporation */ #ifndef _INTEL_GPU_COMMANDS_H_ #define _INTEL_GPU_COMMANDS_H_ #include <linux/bitops.h> /* * Target address alignments required for GPU access e.g. * MI_STORE_DWORD_IMM. */ #define alignof_dword … #define alignof_qword … /* * Instruction field definitions used by the command parser */ #define INSTR_CLIENT_SHIFT … #define INSTR_MI_CLIENT … #define INSTR_BC_CLIENT … #define INSTR_GSC_CLIENT … #define INSTR_RC_CLIENT … #define INSTR_SUBCLIENT_SHIFT … #define INSTR_SUBCLIENT_MASK … #define INSTR_MEDIA_SUBCLIENT … #define INSTR_26_TO_24_MASK … #define INSTR_26_TO_24_SHIFT … #define __INSTR(client) … /* * Memory interface instructions used by the kernel */ #define MI_INSTR(opcode, flags) … /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ #define MI_GLOBAL_GTT … #define MI_NOOP … #define MI_SET_PREDICATE … #define MI_SET_PREDICATE_DISABLE … #define MI_USER_INTERRUPT … #define MI_WAIT_FOR_EVENT … #define MI_WAIT_FOR_OVERLAY_FLIP … #define MI_WAIT_FOR_PLANE_B_FLIP … #define MI_WAIT_FOR_PLANE_A_FLIP … #define MI_WAIT_FOR_PLANE_A_SCANLINES … #define MI_FLUSH … #define MI_READ_FLUSH … #define MI_EXE_FLUSH … #define MI_NO_WRITE_FLUSH … #define MI_SCENE_COUNT … #define MI_END_SCENE … #define MI_INVALIDATE_ISP … #define MI_REPORT_HEAD … #define MI_ARB_ON_OFF … #define MI_ARB_ENABLE … #define MI_ARB_DISABLE … #define MI_BATCH_BUFFER_END … #define MI_SUSPEND_FLUSH … #define MI_SUSPEND_FLUSH_EN … #define MI_SET_APPID … #define MI_SET_APPID_SESSION_ID(x) … #define MI_OVERLAY_FLIP … #define MI_OVERLAY_CONTINUE … #define MI_OVERLAY_ON … #define MI_OVERLAY_OFF … #define MI_LOAD_SCAN_LINES_INCL … #define MI_DISPLAY_FLIP … #define MI_DISPLAY_FLIP_I915 … #define MI_DISPLAY_FLIP_PLANE(n) … /* IVB has funny definitions for which plane to flip. */ #define MI_DISPLAY_FLIP_IVB_PLANE_A … #define MI_DISPLAY_FLIP_IVB_PLANE_B … #define MI_DISPLAY_FLIP_IVB_SPRITE_A … #define MI_DISPLAY_FLIP_IVB_SPRITE_B … #define MI_DISPLAY_FLIP_IVB_PLANE_C … #define MI_DISPLAY_FLIP_IVB_SPRITE_C … /* SKL ones */ #define MI_DISPLAY_FLIP_SKL_PLANE_1_A … #define MI_DISPLAY_FLIP_SKL_PLANE_1_B … #define MI_DISPLAY_FLIP_SKL_PLANE_1_C … #define MI_DISPLAY_FLIP_SKL_PLANE_2_A … #define MI_DISPLAY_FLIP_SKL_PLANE_2_B … #define MI_DISPLAY_FLIP_SKL_PLANE_2_C … #define MI_DISPLAY_FLIP_SKL_PLANE_3_A … #define MI_DISPLAY_FLIP_SKL_PLANE_3_B … #define MI_DISPLAY_FLIP_SKL_PLANE_3_C … #define MI_SEMAPHORE_MBOX … #define MI_SEMAPHORE_GLOBAL_GTT … #define MI_SEMAPHORE_UPDATE … #define MI_SEMAPHORE_COMPARE … #define MI_SEMAPHORE_REGISTER … #define MI_SEMAPHORE_SYNC_VR … #define MI_SEMAPHORE_SYNC_VER … #define MI_SEMAPHORE_SYNC_BR … #define MI_SEMAPHORE_SYNC_BV … #define MI_SEMAPHORE_SYNC_VEV … #define MI_SEMAPHORE_SYNC_RV … #define MI_SEMAPHORE_SYNC_RB … #define MI_SEMAPHORE_SYNC_VEB … #define MI_SEMAPHORE_SYNC_VB … #define MI_SEMAPHORE_SYNC_BVE … #define MI_SEMAPHORE_SYNC_VVE … #define MI_SEMAPHORE_SYNC_RVE … #define MI_SEMAPHORE_SYNC_INVALID … #define MI_SEMAPHORE_SYNC_MASK … #define MI_SET_CONTEXT … #define MI_MM_SPACE_GTT … #define MI_MM_SPACE_PHYSICAL … #define MI_SAVE_EXT_STATE_EN … #define MI_RESTORE_EXT_STATE_EN … #define MI_FORCE_RESTORE … #define MI_RESTORE_INHIBIT … #define HSW_MI_RS_SAVE_STATE_EN … #define HSW_MI_RS_RESTORE_STATE_EN … #define MI_SEMAPHORE_SIGNAL … #define MI_SEMAPHORE_TARGET(engine) … #define MI_SEMAPHORE_WAIT … #define MI_SEMAPHORE_WAIT_TOKEN … #define MI_SEMAPHORE_REGISTER_POLL … #define MI_SEMAPHORE_POLL … #define MI_SEMAPHORE_SAD_GT_SDD … #define MI_SEMAPHORE_SAD_GTE_SDD … #define MI_SEMAPHORE_SAD_LT_SDD … #define MI_SEMAPHORE_SAD_LTE_SDD … #define MI_SEMAPHORE_SAD_EQ_SDD … #define MI_SEMAPHORE_SAD_NEQ_SDD … #define MI_SEMAPHORE_TOKEN_MASK … #define MI_SEMAPHORE_TOKEN_SHIFT … #define MI_STORE_DATA_IMM … #define MI_STORE_DWORD_IMM … #define MI_STORE_DWORD_IMM_GEN4 … #define MI_STORE_QWORD_IMM_GEN8 … #define MI_MEM_VIRTUAL … #define MI_USE_GGTT … #define MI_STORE_DWORD_INDEX … #define MI_ATOMIC … #define MI_ATOMIC_INLINE … #define MI_ATOMIC_GLOBAL_GTT … #define MI_ATOMIC_INLINE_DATA … #define MI_ATOMIC_CS_STALL … #define MI_ATOMIC_MOVE … /* * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw * simply ignores the register load under certain conditions. * - One can actually load arbitrary many arbitrary registers: Simply issue x * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! */ #define MI_LOAD_REGISTER_IMM(x) … /* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */ #define MI_LRI_LRM_CS_MMIO … #define MI_LRI_MMIO_REMAP_EN … #define MI_LRI_FORCE_POSTED … #define MI_LOAD_REGISTER_IMM_MAX_REGS … #define MI_STORE_REGISTER_MEM … #define MI_STORE_REGISTER_MEM_GEN8 … #define MI_SRM_LRM_GLOBAL_GTT … #define MI_FLUSH_DW … #define MI_FLUSH_DW_PROTECTED_MEM_EN … #define MI_FLUSH_DW_STORE_INDEX … #define MI_INVALIDATE_TLB … #define MI_FLUSH_DW_CCS … #define MI_FLUSH_DW_OP_STOREDW … #define MI_FLUSH_DW_OP_MASK … #define MI_FLUSH_DW_LLC … #define MI_FLUSH_DW_NOTIFY … #define MI_INVALIDATE_BSD … #define MI_FLUSH_DW_USE_GTT … #define MI_FLUSH_DW_USE_PPGTT … #define MI_LOAD_REGISTER_MEM … #define MI_LOAD_REGISTER_MEM_GEN8 … #define MI_LOAD_REGISTER_REG … #define MI_LRR_SOURCE_CS_MMIO … #define MI_BATCH_BUFFER … #define MI_BATCH_NON_SECURE … /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ #define MI_BATCH_NON_SECURE_I965 … #define MI_BATCH_PPGTT_HSW … #define MI_BATCH_NON_SECURE_HSW … #define MI_BATCH_BUFFER_START … #define MI_BATCH_GTT … #define MI_BATCH_BUFFER_START_GEN8 … #define MI_BATCH_RESOURCE_STREAMER … #define MI_BATCH_PREDICATE … #define MI_OPCODE(x) … #define IS_MI_LRI_CMD(x) … #define MI_LRI_LEN(x) … /* * 3D instructions used by the kernel */ #define GFX_INSTR(opcode, flags) … #define GEN9_MEDIA_POOL_STATE … #define GEN9_MEDIA_POOL_ENABLE … #define GFX_OP_RASTER_RULES … #define GFX_OP_SCISSOR … #define SC_UPDATE_SCISSOR … #define SC_ENABLE_MASK … #define SC_ENABLE … #define GFX_OP_LOAD_INDIRECT … #define GFX_OP_SCISSOR_INFO … #define SCI_YMIN_MASK … #define SCI_XMIN_MASK … #define SCI_YMAX_MASK … #define SCI_XMAX_MASK … #define GFX_OP_SCISSOR_ENABLE … #define GFX_OP_SCISSOR_RECT … #define GFX_OP_COLOR_FACTOR … #define GFX_OP_STIPPLE … #define GFX_OP_MAP_INFO … #define GFX_OP_DESTBUFFER_VARS … #define GFX_OP_DESTBUFFER_INFO … #define GFX_OP_DRAWRECT_INFO … #define GFX_OP_DRAWRECT_INFO_I965 … #define CMD_3DSTATE_MESH_CONTROL … #define XY_CTRL_SURF_INSTR_SIZE … #define MI_FLUSH_DW_SIZE … #define XY_CTRL_SURF_COPY_BLT … #define SRC_ACCESS_TYPE_SHIFT … #define DST_ACCESS_TYPE_SHIFT … #define CCS_SIZE_MASK … #define CCS_SIZE_SHIFT … #define XY_CTRL_SURF_MOCS_MASK … #define NUM_CCS_BYTES_PER_BLOCK … #define NUM_BYTES_PER_CCS_BYTE … #define NUM_CCS_BLKS_PER_XFER … #define INDIRECT_ACCESS … #define DIRECT_ACCESS … #define COLOR_BLT_CMD … #define XY_COLOR_BLT_CMD … #define XY_FAST_COLOR_BLT_CMD … #define XY_FAST_COLOR_BLT_DEPTH_32 … #define XY_FAST_COLOR_BLT_DW … #define XY_FAST_COLOR_BLT_MOCS_MASK … #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT … #define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK … #define XY_FAST_COPY_BLT_D0_DST_TILING_MASK … #define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) … #define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) … #define LINEAR … #define TILE_X … #define XMAJOR … #define YMAJOR … #define TILE_64 … #define XY_FAST_COPY_BLT_D1_SRC_TILE4 … #define XY_FAST_COPY_BLT_D1_DST_TILE4 … #define BLIT_CCTL_SRC_MOCS_MASK … #define BLIT_CCTL_DST_MOCS_MASK … /* Note: MOCS value = (index << 1) */ #define BLIT_CCTL_SRC_MOCS(idx) … #define BLIT_CCTL_DST_MOCS(idx) … #define SRC_COPY_BLT_CMD … #define GEN9_XY_FAST_COPY_BLT_CMD … #define XY_SRC_COPY_BLT_CMD … #define XY_MONO_SRC_COPY_IMM_BLT … #define BLT_WRITE_A … #define BLT_WRITE_RGB … #define BLT_WRITE_RGBA … #define BLT_DEPTH_8 … #define BLT_DEPTH_16_565 … #define BLT_DEPTH_16_1555 … #define BLT_DEPTH_32 … #define BLT_ROP_SRC_COPY … #define BLT_ROP_COLOR_COPY … #define XY_SRC_COPY_BLT_SRC_TILED … #define XY_SRC_COPY_BLT_DST_TILED … #define CMD_OP_DISPLAYBUFFER_INFO … #define ASYNC_FLIP … #define DISPLAY_PLANE_A … #define DISPLAY_PLANE_B … #define GFX_OP_PIPE_CONTROL(len) … #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE … #define PIPE_CONTROL_TILE_CACHE_FLUSH … #define PIPE_CONTROL_FLUSH_L3 … #define PIPE_CONTROL_AMFS_FLUSH … #define PIPE_CONTROL_GLOBAL_GTT_IVB … #define PIPE_CONTROL_MMIO_WRITE … #define PIPE_CONTROL_STORE_DATA_INDEX … #define PIPE_CONTROL_CS_STALL … #define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET … #define PIPE_CONTROL_TLB_INVALIDATE … #define PIPE_CONTROL_PSD_SYNC … #define PIPE_CONTROL_MEDIA_STATE_CLEAR … #define PIPE_CONTROL_WRITE_TIMESTAMP … #define PIPE_CONTROL_QW_WRITE … #define PIPE_CONTROL_POST_SYNC_OP_MASK … #define PIPE_CONTROL_DEPTH_STALL … #define PIPE_CONTROL_CCS_FLUSH … #define PIPE_CONTROL_WRITE_FLUSH … #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH … #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE … #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE … #define PIPE_CONTROL_INDIRECT_STATE_DISABLE … #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH … #define PIPE_CONTROL_NOTIFY … #define PIPE_CONTROL_FLUSH_ENABLE … #define PIPE_CONTROL_DC_FLUSH_ENABLE … #define PIPE_CONTROL_VF_CACHE_INVALIDATE … #define PIPE_CONTROL_CONST_CACHE_INVALIDATE … #define PIPE_CONTROL_STATE_CACHE_INVALIDATE … #define PIPE_CONTROL_STALL_AT_SCOREBOARD … #define PIPE_CONTROL_DEPTH_CACHE_FLUSH … #define PIPE_CONTROL_GLOBAL_GTT … /* * 3D-related flags that can't be set on _engines_ that lack access to the 3D * pipeline (i.e., CCS engines). */ #define PIPE_CONTROL_3D_ENGINE_FLAGS … /* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */ #define PIPE_CONTROL_3D_ARCH_FLAGS … #define MI_MATH(x) … #define MI_MATH_INSTR(opcode, op1, op2) … /* Opcodes for MI_MATH_INSTR */ #define MI_MATH_NOOP … #define MI_MATH_LOAD(op1, op2) … #define MI_MATH_LOADINV(op1, op2) … #define MI_MATH_LOAD0(op1) … #define MI_MATH_LOAD1(op1) … #define MI_MATH_ADD … #define MI_MATH_SUB … #define MI_MATH_AND … #define MI_MATH_OR … #define MI_MATH_XOR … #define MI_MATH_STORE(op1, op2) … #define MI_MATH_STOREINV(op1, op2) … /* Registers used as operands in MI_MATH_INSTR */ #define MI_MATH_REG(x) … #define MI_MATH_REG_SRCA … #define MI_MATH_REG_SRCB … #define MI_MATH_REG_ACCU … #define MI_MATH_REG_ZF … #define MI_MATH_REG_CF … /* * Media instructions used by the kernel */ #define MEDIA_INSTR(pipe, op, sub_op, flags) … #define MFX_WAIT … #define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG … #define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG … #define CRYPTO_KEY_EXCHANGE … /* * Commands used only by the command parser */ #define MI_SET_PREDICATE … #define MI_ARB_CHECK … #define MI_RS_CONTROL … #define MI_URB_ATOMIC_ALLOC … #define MI_PREDICATE … #define MI_RS_CONTEXT … #define MI_TOPOLOGY_FILTER … #define MI_LOAD_SCAN_LINES_EXCL … #define MI_URB_CLEAR … #define MI_UPDATE_GTT … #define MI_CLFLUSH … #define MI_REPORT_PERF_COUNT … #define MI_REPORT_PERF_COUNT_GGTT … #define MI_RS_STORE_DATA_IMM … #define MI_LOAD_URB_MEM … #define MI_STORE_URB_MEM … #define MI_CONDITIONAL_BATCH_BUFFER_END … #define MI_DO_COMPARE … #define STATE_BASE_ADDRESS … #define BASE_ADDRESS_MODIFY … #define PIPELINE_SELECT … #define PIPELINE_SELECT_MEDIA … #define GFX_OP_3DSTATE_VF_STATISTICS … #define MEDIA_VFE_STATE … #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK … #define MEDIA_INTERFACE_DESCRIPTOR_LOAD … #define MEDIA_OBJECT … #define GPGPU_OBJECT … #define GPGPU_WALKER … #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS … #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS … #define GFX_OP_3DSTATE_SO_DECL_LIST … #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS … #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS … #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS … #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS … #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS … #define COLOR_BLT … #define SRC_COPY_BLT … #define GSC_INSTR(opcode, data, flags) … #define GSC_FW_LOAD … #define HECI1_FW_LIMIT_VALID … #define GSC_HECI_CMD_PKT … /* * Used to convert any address to canonical form. * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS, * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the * addresses to be in a canonical form: * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct * canonical form [63:48] == [47]." */ #define GEN8_HIGH_ADDRESS_BIT … static inline u64 gen8_canonical_addr(u64 address) { … } static inline u64 gen8_noncanonical_addr(u64 address) { … } static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags) { … } #endif /* _INTEL_GPU_COMMANDS_H_ */
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