linux/drivers/gpu/drm/i915/gt/gen6_engine_cs.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2020 Intel Corporation
 */

#include "gen6_engine_cs.h"
#include "intel_engine.h"
#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "intel_gt_pm_irq.h"
#include "intel_ring.h"

#define HWS_SCRATCH_ADDR …

/*
 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 * implementing two workarounds on gen6.  From section 1.4.7.1
 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 *
 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 * produced by non-pipelined state commands), software needs to first
 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 * 0.
 *
 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 *
 * And the workaround for these two requires this workaround first:
 *
 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 * BEFORE the pipe-control with a post-sync op and no write-cache
 * flushes.
 *
 * And this last workaround is tricky because of the requirements on
 * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 * volume 2 part 1:
 *
 *     "1 of the following must also be set:
 *      - Render Target Cache Flush Enable ([12] of DW1)
 *      - Depth Cache Flush Enable ([0] of DW1)
 *      - Stall at Pixel Scoreboard ([1] of DW1)
 *      - Depth Stall ([13] of DW1)
 *      - Post-Sync Operation ([13] of DW1)
 *      - Notify Enable ([8] of DW1)"
 *
 * The cache flushes require the workaround flush that triggered this
 * one, so we can't use it.  Depth stall would trigger the same.
 * Post-sync nonzero is what triggered this second workaround, so we
 * can't use that one either.  Notify enable is IRQs, which aren't
 * really our business.  That leaves only stall at scoreboard.
 */
static int
gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
{ … }

int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode)
{ … }

u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{ … }

static int mi_flush_dw(struct i915_request *rq, u32 flags)
{ … }

static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
{ … }

int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode)
{ … }

int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode)
{ … }

int gen6_emit_bb_start(struct i915_request *rq,
		       u64 offset, u32 len,
		       unsigned int dispatch_flags)
{ … }

int
hsw_emit_bb_start(struct i915_request *rq,
		  u64 offset, u32 len,
		  unsigned int dispatch_flags)
{ … }

static int gen7_stall_cs(struct i915_request *rq)
{ … }

int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode)
{ … }

u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{ … }

u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
{ … }

#define GEN7_XCS_WA …
u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
{ … }
#undef GEN7_XCS_WA

void gen6_irq_enable(struct intel_engine_cs *engine)
{ … }

void gen6_irq_disable(struct intel_engine_cs *engine)
{ … }

void hsw_irq_enable_vecs(struct intel_engine_cs *engine)
{ … }

void hsw_irq_disable_vecs(struct intel_engine_cs *engine)
{ … }