linux/drivers/gpu/drm/i915/gt/intel_lrc.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2014 Intel Corporation
 */

#ifndef __INTEL_LRC_H__
#define __INTEL_LRC_H__

#include "i915_priolist_types.h"

#include <linux/bitfield.h>
#include <linux/types.h>

#include "intel_context.h"

struct drm_i915_gem_object;
struct i915_gem_ww_ctx;
struct intel_engine_cs;
struct intel_ring;
struct kref;

/* At the start of the context image is its per-process HWS page */
#define LRC_PPHWSP_PN …
#define LRC_PPHWSP_SZ …
/* After the PPHWSP we have the logical state for the context */
#define LRC_STATE_PN …
#define LRC_STATE_OFFSET …

/* Space within PPHWSP reserved to be used as scratch */
#define LRC_PPHWSP_SCRATCH …
#define LRC_PPHWSP_SCRATCH_ADDR …

void lrc_init_wa_ctx(struct intel_engine_cs *engine);
void lrc_fini_wa_ctx(struct intel_engine_cs *engine);

int lrc_alloc(struct intel_context *ce,
	      struct intel_engine_cs *engine);
void lrc_reset(struct intel_context *ce);
void lrc_fini(struct intel_context *ce);
void lrc_destroy(struct kref *kref);

int
lrc_pre_pin(struct intel_context *ce,
	    struct intel_engine_cs *engine,
	    struct i915_gem_ww_ctx *ww,
	    void **vaddr);
int
lrc_pin(struct intel_context *ce,
	struct intel_engine_cs *engine,
	void *vaddr);
void lrc_unpin(struct intel_context *ce);
void lrc_post_unpin(struct intel_context *ce);

void lrc_init_state(struct intel_context *ce,
		    struct intel_engine_cs *engine,
		    void *state);

void lrc_init_regs(const struct intel_context *ce,
		   const struct intel_engine_cs *engine,
		   bool clear);
void lrc_reset_regs(const struct intel_context *ce,
		    const struct intel_engine_cs *engine);

u32 lrc_update_regs(const struct intel_context *ce,
		    const struct intel_engine_cs *engine,
		    u32 head);
void lrc_update_offsets(struct intel_context *ce,
			struct intel_engine_cs *engine);

void lrc_check_regs(const struct intel_context *ce,
		    const struct intel_engine_cs *engine,
		    const char *when);

void lrc_update_runtime(struct intel_context *ce);

enum { … };

enum { … };

#define CTX_GTT_ADDRESS_MASK …
#define GEN8_CTX_VALID …
#define GEN8_CTX_FORCE_PD_RESTORE …
#define GEN8_CTX_FORCE_RESTORE …
#define GEN8_CTX_L3LLC_COHERENT …
#define GEN8_CTX_PRIVILEGE …
#define GEN8_CTX_ADDRESSING_MODE_SHIFT …
#define GEN12_CTX_PRIORITY_MASK …
#define GEN12_CTX_PRIORITY_HIGH …
#define GEN12_CTX_PRIORITY_NORMAL …
#define GEN12_CTX_PRIORITY_LOW …
#define GEN8_CTX_ID_SHIFT …
#define GEN8_CTX_ID_WIDTH …
#define GEN11_SW_CTX_ID_SHIFT …
#define GEN11_SW_CTX_ID_WIDTH …
#define GEN11_ENGINE_CLASS_SHIFT …
#define GEN11_ENGINE_CLASS_WIDTH …
#define GEN11_ENGINE_INSTANCE_SHIFT …
#define GEN11_ENGINE_INSTANCE_WIDTH …
#define XEHP_SW_CTX_ID_SHIFT …
#define XEHP_SW_CTX_ID_WIDTH …
#define XEHP_SW_COUNTER_SHIFT …
#define XEHP_SW_COUNTER_WIDTH …
#define GEN12_GUC_SW_CTX_ID_SHIFT …
#define GEN12_GUC_SW_CTX_ID_WIDTH …

static inline void lrc_runtime_start(struct intel_context *ce)
{ … }

static inline void lrc_runtime_stop(struct intel_context *ce)
{ … }

#define DG2_PREDICATE_RESULT_WA …
#define DG2_PREDICATE_RESULT_BB …

u32 lrc_indirect_bb(const struct intel_context *ce);

#endif /* __INTEL_LRC_H__ */