linux/drivers/gpu/drm/i915/gt/gen2_engine_cs.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2020 Intel Corporation
 */

#include "gen2_engine_cs.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_engine.h"
#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "intel_ring.h"

int gen2_emit_flush(struct i915_request *rq, u32 mode)
{ … }

int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
{ … }

int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
{ … }

static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
				   int flush, int post)
{ … }

u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{ … }

u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{ … }

/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
#define I830_BATCH_LIMIT …
#define I830_TLB_ENTRIES …
#define I830_WA_SIZE …
int i830_emit_bb_start(struct i915_request *rq,
		       u64 offset, u32 len,
		       unsigned int dispatch_flags)
{ … }

int gen3_emit_bb_start(struct i915_request *rq,
		       u64 offset, u32 len,
		       unsigned int dispatch_flags)
{ … }

int gen4_emit_bb_start(struct i915_request *rq,
		       u64 offset, u32 length,
		       unsigned int dispatch_flags)
{ … }

void gen2_irq_enable(struct intel_engine_cs *engine)
{ … }

void gen2_irq_disable(struct intel_engine_cs *engine)
{ … }

void gen3_irq_enable(struct intel_engine_cs *engine)
{ … }

void gen3_irq_disable(struct intel_engine_cs *engine)
{ … }

void gen5_irq_enable(struct intel_engine_cs *engine)
{ … }

void gen5_irq_disable(struct intel_engine_cs *engine)
{ … }