/* SPDX-License-Identifier: MIT */ /* * Copyright © 2014-2018 Intel Corporation */ #ifndef _INTEL_LRC_REG_H_ #define _INTEL_LRC_REG_H_ #include <linux/types.h> #define CTX_DESC_FORCE_RESTORE … /* GEN8 to GEN12 Reg State Context */ #define CTX_CONTEXT_CONTROL … #define CTX_RING_HEAD … #define CTX_RING_TAIL … #define CTX_RING_START … #define CTX_RING_CTL … #define CTX_BB_STATE … #define CTX_TIMESTAMP … #define CTX_PDP3_UDW … #define CTX_PDP3_LDW … #define CTX_PDP2_UDW … #define CTX_PDP2_LDW … #define CTX_PDP1_UDW … #define CTX_PDP1_LDW … #define CTX_PDP0_UDW … #define CTX_PDP0_LDW … #define CTX_R_PWR_CLK_STATE … #define GEN9_CTX_RING_MI_MODE … #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) … #define ASSIGN_CTX_PML4(ppgtt, reg_state) … #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT … #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT … #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT … #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT … #define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT … #define GEN8_EXECLISTS_STATUS_BUF … #define GEN11_EXECLISTS_STATUS_BUF2 … /* * The docs specify that the write pointer wraps around after 5h, "After status * is written out to the last available status QW at offset 5h, this pointer * wraps to 0." * * Therefore, one must infer than even though there are 3 bits available, 6 and * 7 appear to be * reserved. */ #define GEN8_CSB_ENTRIES … #define GEN8_CSB_PTR_MASK … #define GEN8_CSB_READ_PTR_MASK … #define GEN8_CSB_WRITE_PTR_MASK … #define GEN11_CSB_ENTRIES … #define GEN11_CSB_PTR_MASK … #define GEN11_CSB_READ_PTR_MASK … #define GEN11_CSB_WRITE_PTR_MASK … #define MAX_CONTEXT_HW_ID … #define GEN11_MAX_CONTEXT_HW_ID … /* in Gen12 ID 0x7FF is reserved to indicate idle */ #define GEN12_MAX_CONTEXT_HW_ID … /* in Xe_HP ID 0xFFFF is reserved to indicate "invalid context" */ #define XEHP_MAX_CONTEXT_HW_ID … #endif /* _INTEL_LRC_REG_H_ */
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