// SPDX-License-Identifier: MIT /* * Copyright © 2022 Intel Corporation */ #include "i915_drv.h" #include "intel_gt.h" #include "intel_gt_mcr.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" /** * DOC: GT Multicast/Replicated (MCR) Register Support * * Some GT registers are designed as "multicast" or "replicated" registers: * multiple instances of the same register share a single MMIO offset. MCR * registers are generally used when the hardware needs to potentially track * independent values of a register per hardware unit (e.g., per-subslice, * per-L3bank, etc.). The specific types of replication that exist vary * per-platform. * * MMIO accesses to MCR registers are controlled according to the settings * programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR * registers can be done in either a (i.e., a single write updates all * instances of the register to the same value) or unicast (a write updates only * one specific instance). Reads of MCR registers always operate in a unicast * manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. * Selection of a specific MCR instance for unicast operations is referred to * as "steering." * * If MCR register operations are steered toward a hardware unit that is * fused off or currently powered down due to power gating, the MMIO operation * is "terminated" by the hardware. Terminated read operations will return a * value of zero and terminated unicast write operations will be silently * ignored. */ #define HAS_MSLICE_STEERING(i915) … static const char * const intel_steering_types[] = …; static const struct intel_mmio_range icl_l3bank_steering_table[] = …; /* * Although the bspec lists more "MSLICE" ranges than shown here, some of those * are of a "GAM" subclass that has special rules. Thus we use a separate * GAM table farther down for those. */ static const struct intel_mmio_range dg2_mslice_steering_table[] = …; static const struct intel_mmio_range dg2_lncf_steering_table[] = …; static const struct intel_mmio_range xelpg_instance0_steering_table[] = …; static const struct intel_mmio_range xelpg_l3bank_steering_table[] = …; /* DSS steering is used for SLICE ranges as well */ static const struct intel_mmio_range xelpg_dss_steering_table[] = …; static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = …; void intel_gt_mcr_init(struct intel_gt *gt) { … } /* * Although the rest of the driver should use MCR-specific functions to * read/write MCR registers, we still use the regular intel_uncore_* functions * internally to implement those, so we need a way for the functions in this * file to "cast" an i915_mcr_reg_t into an i915_reg_t. */ static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr) { … } /* * rw_with_mcr_steering_fw - Access a register with specific MCR steering * @gt: GT to read register from * @reg: register being accessed * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access * @group: group number (documented as "sliceid" on older platforms) * @instance: instance number (documented as "subsliceid" on older platforms) * @value: register value to be written (ignored for read) * * Context: The caller must hold the MCR lock * Return: 0 for write access. register value for read access. * * Caller needs to make sure the relevant forcewake wells are up. */ static u32 rw_with_mcr_steering_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u8 rw_flag, int group, int instance, u32 value) { … } static u32 rw_with_mcr_steering(struct intel_gt *gt, i915_mcr_reg_t reg, u8 rw_flag, int group, int instance, u32 value) { … } /** * intel_gt_mcr_lock - Acquire MCR steering lock * @gt: GT structure * @flags: storage to save IRQ flags to * * Performs locking to protect the steering for the duration of an MCR * operation. On MTL and beyond, a hardware lock will also be taken to * serialize access not only for the driver, but also for external hardware and * firmware agents. * * Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this * function is called, although it may be acquired after this * function call. */ void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags) __acquires(>->mcr_lock) { … } /** * intel_gt_mcr_unlock - Release MCR steering lock * @gt: GT structure * @flags: IRQ flags to restore * * Releases the lock acquired by intel_gt_mcr_lock(). * * Context: Releases gt->mcr_lock */ void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags) __releases(>->mcr_lock) { … } /** * intel_gt_mcr_lock_sanitize - Sanitize MCR steering lock * @gt: GT structure * * This will be used to sanitize the initial status of the hardware lock * during driver load and resume since there won't be any concurrent access * from other agents at those times, but it's possible that boot firmware * may have left the lock in a bad state. * */ void intel_gt_mcr_lock_sanitize(struct intel_gt *gt) { … } /** * intel_gt_mcr_read - read a specific instance of an MCR register * @gt: GT structure * @reg: the MCR register to read * @group: the MCR group * @instance: the MCR instance * * Context: Takes and releases gt->mcr_lock * * Returns the value read from an MCR register after steering toward a specific * group/instance. */ u32 intel_gt_mcr_read(struct intel_gt *gt, i915_mcr_reg_t reg, int group, int instance) { … } /** * intel_gt_mcr_unicast_write - write a specific instance of an MCR register * @gt: GT structure * @reg: the MCR register to write * @value: value to write * @group: the MCR group * @instance: the MCR instance * * Write an MCR register in unicast mode after steering toward a specific * group/instance. * * Context: Calls a function that takes and releases gt->mcr_lock */ void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, int group, int instance) { … } /** * intel_gt_mcr_multicast_write - write a value to all instances of an MCR register * @gt: GT structure * @reg: the MCR register to write * @value: value to write * * Write an MCR register in multicast mode to update all instances. * * Context: Takes and releases gt->mcr_lock */ void intel_gt_mcr_multicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value) { … } /** * intel_gt_mcr_multicast_write_fw - write a value to all instances of an MCR register * @gt: GT structure * @reg: the MCR register to write * @value: value to write * * Write an MCR register in multicast mode to update all instances. This * function assumes the caller is already holding any necessary forcewake * domains; use intel_gt_mcr_multicast_write() in cases where forcewake should * be obtained automatically. * * Context: The caller must hold gt->mcr_lock. */ void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value) { … } /** * intel_gt_mcr_multicast_rmw - Performs a multicast RMW operations * @gt: GT structure * @reg: the MCR register to read and write * @clear: bits to clear during RMW * @set: bits to set during RMW * * Performs a read-modify-write on an MCR register in a multicast manner. * This operation only makes sense on MCR registers where all instances are * expected to have the same value. The read will target any non-terminated * instance and the write will be applied to all instances. * * This function assumes the caller is already holding any necessary forcewake * domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should * be obtained automatically. * * Context: Calls functions that take and release gt->mcr_lock * * Returns the old (unmodified) value read. */ u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 clear, u32 set) { … } /* * reg_needs_read_steering - determine whether a register read requires * explicit steering * @gt: GT structure * @reg: the register to check steering requirements for * @type: type of multicast steering to check * * Determines whether @reg needs explicit steering of a specific type for * reads. * * Returns false if @reg does not belong to a register range of the given * steering type, or if the default (subslice-based) steering IDs are suitable * for @type steering too. */ static bool reg_needs_read_steering(struct intel_gt *gt, i915_mcr_reg_t reg, enum intel_steering_type type) { … } /* * get_nonterminated_steering - determines valid IDs for a class of MCR steering * @gt: GT structure * @type: multicast register type * @group: Group ID returned * @instance: Instance ID returned * * Determines group and instance values that will steer reads of the specified * MCR class to a non-terminated instance. */ static void get_nonterminated_steering(struct intel_gt *gt, enum intel_steering_type type, u8 *group, u8 *instance) { … } /** * intel_gt_mcr_get_nonterminated_steering - find group/instance values that * will steer a register to a non-terminated instance * @gt: GT structure * @reg: register for which the steering is required * @group: return variable for group steering * @instance: return variable for instance steering * * This function returns a group/instance pair that is guaranteed to work for * read steering of the given register. Note that a value will be returned even * if the register is not replicated and therefore does not actually require * steering. */ void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, i915_mcr_reg_t reg, u8 *group, u8 *instance) { … } /** * intel_gt_mcr_read_any_fw - reads one instance of an MCR register * @gt: GT structure * @reg: register to read * * Reads a GT MCR register. The read will be steered to a non-terminated * instance (i.e., one that isn't fused off or powered down by power gating). * This function assumes the caller is already holding any necessary forcewake * domains; use intel_gt_mcr_read_any() in cases where forcewake should be * obtained automatically. * * Context: The caller must hold gt->mcr_lock. * * Returns the value from a non-terminated instance of @reg. */ u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg) { … } /** * intel_gt_mcr_read_any - reads one instance of an MCR register * @gt: GT structure * @reg: register to read * * Reads a GT MCR register. The read will be steered to a non-terminated * instance (i.e., one that isn't fused off or powered down by power gating). * * Context: Calls a function that takes and releases gt->mcr_lock. * * Returns the value from a non-terminated instance of @reg. */ u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg) { … } static void report_steering_type(struct drm_printer *p, struct intel_gt *gt, enum intel_steering_type type, bool dump_table) { … } void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, bool dump_table) { … } /** * intel_gt_mcr_get_ss_steering - returns the group/instance steering for a SS * @gt: GT structure * @dss: DSS ID to obtain steering for * @group: pointer to storage for steering group ID * @instance: pointer to storage for steering instance ID * * Returns the steering IDs (via the @group and @instance parameters) that * correspond to a specific subslice/DSS ID. */ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, unsigned int *group, unsigned int *instance) { … } /** * intel_gt_mcr_wait_for_reg - wait until MCR register matches expected state * @gt: GT structure * @reg: the register to read * @mask: mask to apply to register value * @value: value to wait for * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait * @slow_timeout_ms: slow timeout in millisecond * * This routine waits until the target register @reg contains the expected * @value after applying the @mask, i.e. it waits until :: * * (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value * * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us * must be not larger than 20,0000 microseconds. * * This function is basically an MCR-friendly version of * __intel_wait_for_register_fw(). Generally this function will only be used * on GAM registers which are a bit special --- although they're MCR registers, * reads (e.g., waiting for status updates) are always directed to the primary * instance. * * Note that this routine assumes the caller holds forcewake asserted, it is * not suitable for very long waits. * * Context: Calls a function that takes and releases gt->mcr_lock * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. */ int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, i915_mcr_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_ms) { … }
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