// SPDX-License-Identifier: MIT /* * Copyright © 2015 Intel Corporation */ #include "i915_drv.h" #include "intel_engine.h" #include "intel_gt.h" #include "intel_gt_mcr.h" #include "intel_gt_regs.h" #include "intel_mocs.h" #include "intel_ring.h" /* structures required */ struct drm_i915_mocs_entry { … }; struct drm_i915_mocs_table { … }; /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ #define _LE_CACHEABILITY(value) … #define _LE_TGT_CACHE(value) … #define LE_LRUM(value) … #define LE_AOM(value) … #define LE_RSC(value) … #define LE_SCC(value) … #define LE_PFM(value) … #define LE_SCF(value) … #define LE_COS(value) … #define LE_SSE(value) … /* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */ #define _L4_CACHEABILITY(value) … #define IG_PAT(value) … /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) … #define L3_SCC(value) … #define _L3_CACHEABILITY(value) … #define L3_GLBGO(value) … #define L3_LKUP(value) … /* Helper defines */ #define GEN9_NUM_MOCS_ENTRIES … #define MTL_NUM_MOCS_ENTRIES … /* (e)LLC caching options */ /* * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means * the same as LE_UC */ #define LE_0_PAGETABLE … #define LE_1_UC … #define LE_2_WT … #define LE_3_WB … /* Target cache */ #define LE_TC_0_PAGETABLE … #define LE_TC_1_LLC … #define LE_TC_2_LLC_ELLC … #define LE_TC_3_LLC_ELLC_ALT … /* L3 caching options */ #define L3_0_DIRECT … #define L3_1_UC … #define L3_2_RESERVED … #define L3_3_WB … /* L4 caching options */ #define L4_0_WB … #define L4_1_WT … #define L4_2_RESERVED … #define L4_3_UC … #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) … /* * MOCS tables * * These are the MOCS tables that are programmed across all the rings. * The control value is programmed to all the rings that support the * MOCS registers. While the l3cc_values are only programmed to the * LNCFCMOCS0 - LNCFCMOCS32 registers. * * These tables are intended to be kept reasonably consistent across * HW platforms, and for ICL+, be identical across OSes. To achieve * that, for Icelake and above, list of entries is published as part * of bspec. * * Entries not part of the following tables are undefined as far as * userspace is concerned and shouldn't be relied upon. For Gen < 12 * they will be initialized to PTE. Gen >= 12 don't have a setting for * PTE and those platforms except TGL/RKL will be initialized L3 WB to * catch accidental use of reserved and unused mocs indexes. * * The last few entries are reserved by the hardware. For ICL+ they * should be initialized according to bspec and never used, for older * platforms they should never be written to. * * NOTE1: These tables are part of bspec and defined as part of hardware * interface for ICL+. For older platforms, they are part of kernel * ABI. It is expected that, for specific hardware platform, existing * entries will remain constant and the table will only be updated by * adding new entries, filling unused positions. * * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS * indices have been set to L3 WB. These reserved entries should never * be used, they may be changed to low performant variants with better * coherency in the future if more entries are needed. * For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC. */ #define GEN9_MOCS_ENTRIES … static const struct drm_i915_mocs_entry skl_mocs_table[] = …; /* NOTE: the LE_TGT_CACHE is not used on Broxton */ static const struct drm_i915_mocs_entry broxton_mocs_table[] = …; #define GEN11_MOCS_ENTRIES … static const struct drm_i915_mocs_entry tgl_mocs_table[] = …; static const struct drm_i915_mocs_entry icl_mocs_table[] = …; static const struct drm_i915_mocs_entry dg1_mocs_table[] = …; static const struct drm_i915_mocs_entry gen12_mocs_table[] = …; static const struct drm_i915_mocs_entry dg2_mocs_table[] = …; static const struct drm_i915_mocs_entry mtl_mocs_table[] = …; enum { … }; static bool has_l3cc(const struct drm_i915_private *i915) { … } static bool has_global_mocs(const struct drm_i915_private *i915) { … } static bool has_mocs(const struct drm_i915_private *i915) { … } static unsigned int get_mocs_settings(struct drm_i915_private *i915, struct drm_i915_mocs_table *table) { … } /* * Get control_value from MOCS entry taking into account when it's not used * then if unused_entries_index is non-zero then its value will be returned * otherwise I915_MOCS_PTE's value is returned in this case. */ static u32 get_entry_control(const struct drm_i915_mocs_table *table, unsigned int index) { … } #define for_each_mocs(mocs, t, i) … static void __init_mocs_table(struct intel_uncore *uncore, const struct drm_i915_mocs_table *table, u32 addr) { … } static u32 mocs_offset(const struct intel_engine_cs *engine) { … } static void init_mocs_table(struct intel_engine_cs *engine, const struct drm_i915_mocs_table *table) { … } /* * Get l3cc_value from MOCS entry taking into account when it's not used * then if unused_entries_index is not zero then its value will be returned * otherwise I915_MOCS_PTE's value is returned in this case. */ static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table, unsigned int index) { … } static u32 l3cc_combine(u16 low, u16 high) { … } #define for_each_l3cc(l3cc, t, i) … static void init_l3cc_table(struct intel_gt *gt, const struct drm_i915_mocs_table *table) { … } void intel_mocs_init_engine(struct intel_engine_cs *engine) { … } static u32 global_mocs_offset(void) { … } void intel_set_mocs_index(struct intel_gt *gt) { … } void intel_mocs_init(struct intel_gt *gt) { … } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftest_mocs.c" #endif
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