intel_rc6.c | Explore in Territory

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2019 Intel Corporation
 */

#include <linux/pm_runtime.h>
#include <linux/string_helpers.h>

#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_vgpu.h"
#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_regs.h"
#include "intel_pcode.h"
#include "intel_rc6.h"

/**
 * DOC: RC6
 *
 * RC6 is a special power stage which allows the GPU to enter an very
 * low-voltage mode when idle, using down to 0V while at this stage.  This
 * stage is entered automatically when the GPU is idle when RC6 support is
 * enabled, and as soon as new workload arises GPU wakes up automatically as
 * well.
 *
 * There are different RC6 modes available in Intel GPU, which differentiate
 * among each other with the latency required to enter and leave RC6 and
 * voltage consumed by the GPU in different states.
 *
 * The combination of the following flags define which states GPU is allowed
 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
 * RC6pp is deepest RC6. Their support by hardware varies according to the
 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
 * which brings the most power savings; deeper states save more power, but
 * require higher latency to switch to and wake up.
 */

static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6)
{ … }

static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc)
{ … }

static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
{ … }

static void gen11_rc6_enable(struct intel_rc6 *rc6)
{ … }

static void gen9_rc6_enable(struct intel_rc6 *rc6)
{ … }

static void gen8_rc6_enable(struct intel_rc6 *rc6)
{ … }

static void gen6_rc6_enable(struct intel_rc6 *rc6)
{ … }

/* Check that the pcbr address is not empty. */
static int chv_rc6_init(struct intel_rc6 *rc6)
{ … }

static int vlv_rc6_init(struct intel_rc6 *rc6)
{ … }

static void chv_rc6_enable(struct intel_rc6 *rc6)
{ … }

static void vlv_rc6_enable(struct intel_rc6 *rc6)
{ … }

bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
{ … }

static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
{ … }

static bool rc6_supported(struct intel_rc6 *rc6)
{ … }

static void rpm_get(struct intel_rc6 *rc6)
{ … }

static void rpm_put(struct intel_rc6 *rc6)
{ … }

static bool pctx_corrupted(struct intel_rc6 *rc6)
{ … }

static void __intel_rc6_disable(struct intel_rc6 *rc6)
{ … }

static void rc6_res_reg_init(struct intel_rc6 *rc6)
{ … }

void intel_rc6_init(struct intel_rc6 *rc6)
{ … }

void intel_rc6_sanitize(struct intel_rc6 *rc6)
{ … }

void intel_rc6_enable(struct intel_rc6 *rc6)
{ … }

void intel_rc6_unpark(struct intel_rc6 *rc6)
{ … }

void intel_rc6_park(struct intel_rc6 *rc6)
{ … }

void intel_rc6_disable(struct intel_rc6 *rc6)
{ … }

void intel_rc6_fini(struct intel_rc6 *rc6)
{ … }

static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
{ … }

u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
{ … }

u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
{ … }

void intel_rc6_print_residency(struct seq_file *m, const char *title,
			       enum intel_rc6_res_type id)
{ … }

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_rc6.c"
#endif
linux/drivers/gpu/drm/i915/gt/intel_rc6.c
