linux/drivers/gpu/drm/i915/gt/intel_tlb.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2023 Intel Corporation
 */

#include "i915_drv.h"
#include "i915_perf_oa_regs.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_mcr.h"
#include "intel_gt_pm.h"
#include "intel_gt_print.h"
#include "intel_gt_regs.h"
#include "intel_tlb.h"
#include "uc/intel_guc.h"

/*
 * HW architecture suggest typical invalidation time at 40us,
 * with pessimistic cases up to 100us and a recommendation to
 * cap at 1ms. We go a bit higher just in case.
 */
#define TLB_INVAL_TIMEOUT_US …
#define TLB_INVAL_TIMEOUT_MS …

/*
 * On Xe_HP the TLB invalidation registers are located at the same MMIO offsets
 * but are now considered MCR registers.  Since they exist within a GAM range,
 * the primary instance of the register rolls up the status from each unit.
 */
static int wait_for_invalidate(struct intel_engine_cs *engine)
{ … }

static void mmio_invalidate_full(struct intel_gt *gt)
{ … }

static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno)
{ … }

void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
{ … }

void intel_gt_init_tlb(struct intel_gt *gt)
{ … }

void intel_gt_fini_tlb(struct intel_gt *gt)
{ … }

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_tlb.c"
#endif