linux/drivers/gpu/drm/i915/gt/selftest_workarounds.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2018 Intel Corporation
 */

#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt.h"
#include "i915_selftest.h"
#include "intel_reset.h"

#include "selftests/igt_flush_test.h"
#include "selftests/igt_reset.h"
#include "selftests/igt_spinner.h"
#include "selftests/intel_scheduler_helpers.h"
#include "selftests/mock_drm.h"

#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"

static const struct wo_register { … } wo_registers[] = …;

struct wa_lists { … };

static int request_add_sync(struct i915_request *rq, int err)
{ … }

static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
{ … }

static void
reference_lists_init(struct intel_gt *gt, struct wa_lists *lists)
{ … }

static void
reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists)
{ … }

static struct drm_i915_gem_object *
read_nonprivs(struct intel_context *ce)
{ … }

static u32
get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
{ … }

static void
print_results(const struct intel_engine_cs *engine, const u32 *results)
{ … }

static int check_whitelist(struct intel_context *ce)
{ … }

static int do_device_reset(struct intel_engine_cs *engine)
{ … }

static int do_engine_reset(struct intel_engine_cs *engine)
{ … }

static int do_guc_reset(struct intel_engine_cs *engine)
{ … }

static int
switch_to_scratch_context(struct intel_engine_cs *engine,
			  struct igt_spinner *spin,
			  struct i915_request **rq)
{ … }

static int check_whitelist_across_reset(struct intel_engine_cs *engine,
					int (*reset)(struct intel_engine_cs *),
					const char *name)
{ … }

static struct i915_vma *create_batch(struct i915_address_space *vm)
{ … }

static u32 reg_write(u32 old, u32 new, u32 rsvd)
{ … }

static bool wo_register(struct intel_engine_cs *engine, u32 reg)
{ … }

static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
{ … }

static bool ro_register(u32 reg)
{ … }

static int whitelist_writable_count(struct intel_engine_cs *engine)
{ … }

static int check_dirty_whitelist(struct intel_context *ce)
{ … }

static int live_dirty_whitelist(void *arg)
{ … }

static int live_reset_whitelist(void *arg)
{ … }

static int read_whitelisted_registers(struct intel_context *ce,
				      struct i915_vma *results)
{ … }

static int scrub_whitelisted_registers(struct intel_context *ce)
{ … }

struct regmask { … };

static bool find_reg(struct drm_i915_private *i915,
		     i915_reg_t reg,
		     const struct regmask *tbl,
		     unsigned long count)
{ … }

static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ … }

static bool result_eq(struct intel_engine_cs *engine,
		      u32 a, u32 b, i915_reg_t reg)
{ … }

static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
{ … }

static bool result_neq(struct intel_engine_cs *engine,
		       u32 a, u32 b, i915_reg_t reg)
{ … }

static int
check_whitelisted_registers(struct intel_engine_cs *engine,
			    struct i915_vma *A,
			    struct i915_vma *B,
			    bool (*fn)(struct intel_engine_cs *engine,
				       u32 a, u32 b,
				       i915_reg_t reg))
{ … }

static int live_isolated_whitelist(void *arg)
{ … }

static bool
verify_wa_lists(struct intel_gt *gt, struct wa_lists *lists,
		const char *str)
{ … }

static int
live_gpu_reset_workarounds(void *arg)
{ … }

static int
live_engine_reset_workarounds(void *arg)
{ … }

int intel_workarounds_live_selftests(struct drm_i915_private *i915)
{ … }