linux/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2021 Intel Corporation
 */

#include <drm/drm_cache.h>
#include <linux/string_helpers.h>

#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_guc_slpc.h"
#include "intel_guc_print.h"
#include "intel_mchbar_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_rps.h"

static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
{ … }

static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
{ … }

static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc *slpc)
{ … }

static bool __detect_slpc_supported(struct intel_guc *guc)
{ … }

static bool __guc_slpc_selected(struct intel_guc *guc)
{ … }

void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
{ … }

static void slpc_mem_set_param(struct slpc_shared_data *data,
			       u32 id, u32 value)
{ … }

static void slpc_mem_set_enabled(struct slpc_shared_data *data,
				 u8 enable_id, u8 disable_id)
{ … }

static void slpc_mem_set_disabled(struct slpc_shared_data *data,
				  u8 enable_id, u8 disable_id)
{ … }

static u32 slpc_get_state(struct intel_guc_slpc *slpc)
{ … }

static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value)
{ … }

static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)
{ … }

static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
{ … }

static bool slpc_is_running(struct intel_guc_slpc *slpc)
{ … }

static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
{ … }

static int slpc_query_task_state(struct intel_guc_slpc *slpc)
{ … }

static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
{ … }

static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
{ … }

static void slpc_boost_work(struct work_struct *work)
{ … }

int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
{ … }

static const char *slpc_global_state_to_string(enum slpc_global_state state)
{ … }

static const char *slpc_get_state_string(struct intel_guc_slpc *slpc)
{ … }

static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
{ … }

static int slpc_reset(struct intel_guc_slpc *slpc)
{ … }

static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
{ … }

static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
{ … }

static void slpc_shared_data_reset(struct slpc_shared_data *data)
{ … }

/**
 * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
 * @slpc: pointer to intel_guc_slpc.
 * @val: frequency (MHz)
 *
 * This function will invoke GuC SLPC action to update the max frequency
 * limit for unslice.
 *
 * Return: 0 on success, non-zero error code on failure.
 */
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
{ … }

/**
 * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
 * @slpc: pointer to intel_guc_slpc.
 * @val: pointer to val which will hold max frequency (MHz)
 *
 * This function will invoke GuC SLPC action to read the max frequency
 * limit for unslice.
 *
 * Return: 0 on success, non-zero error code on failure.
 */
int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
{ … }

int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val)
{ … }

/**
 * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
 * @slpc: pointer to intel_guc_slpc.
 * @val: frequency (MHz)
 *
 * This function will invoke GuC SLPC action to update the min unslice
 * frequency.
 *
 * Return: 0 on success, non-zero error code on failure.
 */
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
{ … }

/**
 * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
 * @slpc: pointer to intel_guc_slpc.
 * @val: pointer to val which will hold min frequency (MHz)
 *
 * This function will invoke GuC SLPC action to read the min frequency
 * limit for unslice.
 *
 * Return: 0 on success, non-zero error code on failure.
 */
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
{ … }

int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val)
{ … }

int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)
{ … }

void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
{ … }

static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
{ … }

static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
{ … }

static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
{ … }

static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
{ … }

static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
{ … }

/*
 * intel_guc_slpc_enable() - Start SLPC
 * @slpc: pointer to intel_guc_slpc.
 *
 * SLPC is enabled by setting up the shared data structure and
 * sending reset event to GuC SLPC. Initial data is setup in
 * intel_guc_slpc_init. Here we send the reset event. We do
 * not currently need a slpc_disable since this is taken care
 * of automatically when a reset/suspend occurs and the GuC
 * CTB is destroyed.
 *
 * Return: 0 on success, non-zero error code on failure.
 */
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
{ … }

int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val)
{ … }

void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
{ … }

int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
{ … }

void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
{ … }