intel_bw.c | Explore in Territory

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2019 Intel Corporation
 */

#include <drm/drm_atomic_state_helper.h>

#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
#include "intel_atomic.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_display_core.h"
#include "intel_display_types.h"
#include "skl_watermark.h"
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"

/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point { … };

#define DEPROGBWPCLIMIT …

struct intel_psf_gv_point { … };

struct intel_qgv_info { … };

static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
					  struct intel_qgv_point *sp,
					  int point)
{ … }

static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
					 struct intel_qgv_point *sp,
					 int point)
{ … }

static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
					    struct intel_psf_gv_point *points)
{ … }

static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
{ … }

static bool is_sagv_enabled(struct drm_i915_private *i915, u16 points_mask)
{ … }

int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
				  u32 points_mask)
{ … }

static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
				   struct intel_qgv_point *sp, int point)
{ … }

static int
intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
			  struct intel_qgv_point *sp,
			  int point)
{ … }

static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
			      struct intel_qgv_info *qi,
			      bool is_y_tile)
{ … }

static int adl_calc_psf_bw(int clk)
{ … }

static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
{ … }

struct intel_sa_info { … };

static const struct intel_sa_info icl_sa_info = …;

static const struct intel_sa_info tgl_sa_info = …;

static const struct intel_sa_info rkl_sa_info = …;

static const struct intel_sa_info adls_sa_info = …;

static const struct intel_sa_info adlp_sa_info = …;

static const struct intel_sa_info mtl_sa_info = …;

static const struct intel_sa_info xe2_hpd_sa_info = …;

static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{ … }

static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{ … }

static void dg2_get_bw_info(struct drm_i915_private *i915)
{ … }

static int xe2_hpd_get_bw_info(struct drm_i915_private *i915,
			       const struct intel_sa_info *sa)
{ … }

static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv,
				     int num_planes, int qgv_point)
{ … }

static unsigned int tgl_max_bw_index(struct drm_i915_private *dev_priv,
				     int num_planes, int qgv_point)
{ … }

static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
			       int psf_gv_point)
{ … }

static unsigned int icl_qgv_bw(struct drm_i915_private *i915,
			       int num_active_planes, int qgv_point)
{ … }

void intel_bw_init_hw(struct drm_i915_private *dev_priv)
{ … }

static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{ … }

static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
{ … }

/* "Maximum Pipe Read Bandwidth" */
static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
{ … }

void intel_bw_crtc_update(struct intel_bw_state *bw_state,
			  const struct intel_crtc_state *crtc_state)
{ … }

static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
					       const struct intel_bw_state *bw_state)
{ … }

static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
				       const struct intel_bw_state *bw_state)
{ … }

struct intel_bw_state *
intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
{ … }

struct intel_bw_state *
intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
{ … }

struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state)
{ … }

static unsigned int icl_max_bw_qgv_point_mask(struct drm_i915_private *i915,
					      int num_active_planes)
{ … }

static u16 icl_prepare_qgv_points_mask(struct drm_i915_private *i915,
				       unsigned int qgv_points,
				       unsigned int psf_points)
{ … }

static unsigned int icl_max_bw_psf_gv_point_mask(struct drm_i915_private *i915)
{ … }

static void icl_force_disable_sagv(struct drm_i915_private *i915,
				   struct intel_bw_state *bw_state)
{ … }

static int mtl_find_qgv_points(struct drm_i915_private *i915,
			       unsigned int data_rate,
			       unsigned int num_active_planes,
			       struct intel_bw_state *new_bw_state)
{ … }

static int icl_find_qgv_points(struct drm_i915_private *i915,
			       unsigned int data_rate,
			       unsigned int num_active_planes,
			       const struct intel_bw_state *old_bw_state,
			       struct intel_bw_state *new_bw_state)
{ … }

static int intel_bw_check_qgv_points(struct drm_i915_private *i915,
				     const struct intel_bw_state *old_bw_state,
				     struct intel_bw_state *new_bw_state)
{ … }

static bool intel_bw_state_changed(struct drm_i915_private *i915,
				   const struct intel_bw_state *old_bw_state,
				   const struct intel_bw_state *new_bw_state)
{ … }

static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
				   struct intel_crtc *crtc,
				   enum plane_id plane_id,
				   const struct skl_ddb_entry *ddb,
				   unsigned int data_rate)
{ … }

static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
				  const struct intel_crtc_state *crtc_state)
{ … }

/* "Maximum Data Buffer Bandwidth" */
static int
intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
			const struct intel_bw_state *bw_state)
{ … }

int intel_bw_min_cdclk(struct drm_i915_private *i915,
		       const struct intel_bw_state *bw_state)
{ … }

int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
			    bool *need_cdclk_calc)
{ … }

static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
{ … }

int intel_bw_atomic_check(struct intel_atomic_state *state)
{ … }

static struct intel_global_state *
intel_bw_duplicate_state(struct intel_global_obj *obj)
{ … }

static void intel_bw_destroy_state(struct intel_global_obj *obj,
				   struct intel_global_state *state)
{ … }

static const struct intel_global_state_funcs intel_bw_funcs = …;

int intel_bw_init(struct drm_i915_private *i915)
{ … }
linux/drivers/gpu/drm/i915/display/intel_bw.c
