/* * Copyright © 2006-2017 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include <linux/time.h> #include <drm/drm_fixed.h> #include "soc/intel_dram.h" #include "hsw_ips.h" #include "i915_reg.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_audio.h" #include "intel_bw.h" #include "intel_cdclk.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_dp.h" #include "intel_display_types.h" #include "intel_mchbar_regs.h" #include "intel_pci_config.h" #include "intel_pcode.h" #include "intel_psr.h" #include "intel_vdsc.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" #include "vlv_sideband.h" /** * DOC: CDCLK / RAWCLK * * The display engine uses several different clocks to do its work. There * are two main clocks involved that aren't directly related to the actual * pixel clock or any symbol/bit clock of the actual output port. These * are the core display clock (CDCLK) and RAWCLK. * * CDCLK clocks most of the display pipe logic, and thus its frequency * must be high enough to support the rate at which pixels are flowing * through the pipes. Downscaling must also be accounted as that increases * the effective pixel rate. * * On several platforms the CDCLK frequency can be changed dynamically * to minimize power consumption for a given display configuration. * Typically changes to the CDCLK frequency require all the display pipes * to be shut down while the frequency is being changed. * * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. * DMC will not change the active CDCLK frequency however, so that part * will still be performed by the driver directly. * * There are multiple components involved in the generation of the CDCLK * frequency: * * - We have the CDCLK PLL, which generates an output clock based on a * reference clock and a ratio parameter. * - The CD2X Divider, which divides the output of the PLL based on a * divisor selected from a set of pre-defined choices. * - The CD2X Squasher, which further divides the output based on a * waveform represented as a sequence of bits where each zero * "squashes out" a clock cycle. * - And, finally, a fixed divider that divides the output frequency by 2. * * As such, the resulting CDCLK frequency can be calculated with the * following formula: * * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 * * , where vco is the frequency generated by the PLL; cd2x_div * represents the CD2X Divider; sq_len and sq_div are the bit length * and the number of high bits for the CD2X Squasher waveform, respectively; * and 2 represents the fixed divider. * * Note that some older platforms do not contain the CD2X Divider * and/or CD2X Squasher, in which case we can ignore their respective * factors in the formula above. * * Several methods exist to change the CDCLK frequency, which ones are * supported depends on the platform: * * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. * - CD2X divider update. Single pipe can be active as the divider update * can be synchronized with the pipe's start of vblank. * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. * - Squash waveform update. Pipes can be active. * - Crawl and squash can also be done back to back. Pipes can be active. * * RAWCLK is a fixed frequency clock, often used by various auxiliary * blocks such as AUX CH or backlight PWM. Hence the only thing we * really need to know about RAWCLK is its frequency so that various * dividers can be programmed correctly. */ struct intel_cdclk_funcs { … }; void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) { … } static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void i85x_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) { … } static void g33_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void pnv_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void gm45_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void hsw_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { … } static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) { … } static void vlv_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) { … } static void vlv_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static void chv_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static int bdw_calc_cdclk(int min_cdclk) { … } static u8 bdw_calc_voltage_level(int cdclk) { … } static void bdw_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static u32 bdw_cdclk_freq_sel(int cdclk) { … } static void bdw_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static int skl_calc_cdclk(int min_cdclk, int vco) { … } static u8 skl_calc_voltage_level(int cdclk) { … } static void skl_dpll0_update(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void skl_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ static int skl_cdclk_decimal(int cdclk) { … } static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco) { … } static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) { … } static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { … } static void skl_dpll0_disable(struct drm_i915_private *dev_priv) { … } static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, int cdclk, int vco) { … } static void skl_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) { … } static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) { … } static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { … } struct intel_cdclk_vals { … }; static const struct intel_cdclk_vals bxt_cdclk_table[] = …; static const struct intel_cdclk_vals glk_cdclk_table[] = …; static const struct intel_cdclk_vals icl_cdclk_table[] = …; static const struct intel_cdclk_vals rkl_cdclk_table[] = …; static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = …; static const struct intel_cdclk_vals adlp_cdclk_table[] = …; static const struct intel_cdclk_vals rplu_cdclk_table[] = …; static const struct intel_cdclk_vals dg2_cdclk_table[] = …; static const struct intel_cdclk_vals mtl_cdclk_table[] = …; static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = …; /* * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 */ static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = …; static const int cdclk_squash_len = …; static int cdclk_squash_divider(u16 waveform) { … } static int cdclk_divider(int cdclk, int vco, u16 waveform) { … } static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { … } static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) { … } static u8 bxt_calc_voltage_level(int cdclk) { … } static u8 calc_voltage_level(int cdclk, int num_voltage_levels, const int voltage_level_max_cdclk[]) { … } static u8 icl_calc_voltage_level(int cdclk) { … } static u8 ehl_calc_voltage_level(int cdclk) { … } static u8 tgl_calc_voltage_level(int cdclk) { … } static u8 rplu_calc_voltage_level(int cdclk) { … } static void icl_readout_refclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void bxt_get_cdclk(struct drm_i915_private *dev_priv, struct intel_cdclk_config *cdclk_config) { … } static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) { … } static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) { … } static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) { … } static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) { … } static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) { … } static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { … } static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, int cdclk, int vco, u16 waveform) { … } static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv, int cdclk) { … } static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) { … } static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) { … } static void dg2_cdclk_squash_program(struct drm_i915_private *i915, u16 waveform) { … } static bool cdclk_pll_is_unknown(unsigned int vco) { … } static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915) { … } static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915) { … } int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, const struct intel_cdclk_config *cdclk_config) { … } static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915, const struct intel_cdclk_config *cdclk_config) { … } static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, const struct intel_cdclk_config *old_cdclk_config, const struct intel_cdclk_config *new_cdclk_config, struct intel_cdclk_config *mid_cdclk_config) { … } static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) { … } static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { … } static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) { … } static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) { … } static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { … } /** * intel_cdclk_init_hw - Initialize CDCLK hardware * @i915: i915 device * * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and * sanitizing the state of the hardware if needed. This is generally done only * during the display core initialization sequence, after which the DMC will * take care of turning CDCLK off/on as needed. */ void intel_cdclk_init_hw(struct drm_i915_private *i915) { … } /** * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware * @i915: i915 device * * Uninitialize CDCLK. This is done only during the display core * uninitialization sequence. */ void intel_cdclk_uninit_hw(struct drm_i915_private *i915) { … } static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { … } static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { … } static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { … } /** * intel_cdclk_clock_changed - Check whether the clock changed * @a: first CDCLK configuration * @b: second CDCLK configuration * * Returns: * True if CDCLK changed in a way that requires re-programming and * False otherwise. */ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { … } /** * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK * configurations requires only a cd2x divider update * @dev_priv: i915 device * @a: first CDCLK configuration * @b: second CDCLK configuration * * Returns: * True if changing between the two CDCLK configurations * can be done with just a cd2x divider update, false if not. */ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { … } /** * intel_cdclk_changed - Determine if two CDCLK configurations are different * @a: first CDCLK configuration * @b: second CDCLK configuration * * Returns: * True if the CDCLK configurations don't match, false if they do. */ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { … } void intel_cdclk_dump_config(struct drm_i915_private *i915, const struct intel_cdclk_config *cdclk_config, const char *context) { … } static void intel_pcode_notify(struct drm_i915_private *i915, u8 voltage_level, u8 active_pipe_count, u16 cdclk, bool cdclk_update_valid, bool pipe_count_update_valid) { … } static void intel_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe, const char *context) { … } static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) { … } static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) { … } bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) { … } /** * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware * @state: intel atomic state * * Program the hardware before updating the HW plane state based on the * new CDCLK state, if necessary. */ void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { … } /** * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware * @state: intel atomic state * * Program the hardware after updating the HW plane state based on the * new CDCLK state, if necessary. */ void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { … } static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) { … } static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) { … } static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) { … } int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) { … } static int intel_compute_min_cdclk(struct intel_atomic_state *state) { … } /* * Account for port clock min voltage level requirements. * This only really does something on DISPLA_VER >= 11 but can be * called on earlier platforms as well. * * Note that this functions assumes that 0 is * the lowest voltage value, and higher values * correspond to increasingly higher voltages. * * Should that relationship no longer hold on * future platforms this code will need to be * adjusted. */ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) { … } static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static int skl_dpll0_vco(struct intel_atomic_state *state) { … } static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) { … } static void intel_cdclk_destroy_state(struct intel_global_obj *obj, struct intel_global_state *state) { … } static const struct intel_global_state_funcs intel_cdclk_funcs = …; struct intel_cdclk_state * intel_atomic_get_cdclk_state(struct intel_atomic_state *state) { … } int intel_cdclk_atomic_check(struct intel_atomic_state *state, bool *need_cdclk_calc) { … } int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) { … } int intel_cdclk_init(struct drm_i915_private *dev_priv) { … } static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, const struct intel_cdclk_state *old_cdclk_state, const struct intel_cdclk_state *new_cdclk_state) { … } int intel_modeset_calc_cdclk(struct intel_atomic_state *state) { … } static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) { … } /** * intel_update_max_cdclk - Determine the maximum support CDCLK frequency * @dev_priv: i915 device * * Determine the maximum CDCLK frequency the platform supports, and also * derive the maximum dot clock frequency the maximum CDCLK frequency * allows. */ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) { … } /** * intel_update_cdclk - Determine the current CDCLK frequency * @dev_priv: i915 device * * Determine the current CDCLK frequency. */ void intel_update_cdclk(struct drm_i915_private *dev_priv) { … } static int dg1_rawclk(struct drm_i915_private *dev_priv) { … } static int cnp_rawclk(struct drm_i915_private *dev_priv) { … } static int pch_rawclk(struct drm_i915_private *dev_priv) { … } static int vlv_hrawclk(struct drm_i915_private *dev_priv) { … } static int i9xx_hrawclk(struct drm_i915_private *i915) { … } /** * intel_read_rawclk - Determine the current RAWCLK frequency * @dev_priv: i915 device * * Determine the current RAWCLK frequency. RAWCLK is a fixed * frequency clock so this needs to done only once. */ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) { … } static int i915_cdclk_info_show(struct seq_file *m, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); void intel_cdclk_debugfs_register(struct drm_i915_private *i915) { … } static const struct intel_cdclk_funcs rplu_cdclk_funcs = …; static const struct intel_cdclk_funcs tgl_cdclk_funcs = …; static const struct intel_cdclk_funcs ehl_cdclk_funcs = …; static const struct intel_cdclk_funcs icl_cdclk_funcs = …; static const struct intel_cdclk_funcs bxt_cdclk_funcs = …; static const struct intel_cdclk_funcs skl_cdclk_funcs = …; static const struct intel_cdclk_funcs bdw_cdclk_funcs = …; static const struct intel_cdclk_funcs chv_cdclk_funcs = …; static const struct intel_cdclk_funcs vlv_cdclk_funcs = …; static const struct intel_cdclk_funcs hsw_cdclk_funcs = …; /* SNB, IVB, 965G, 945G */ static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = …; static const struct intel_cdclk_funcs ilk_cdclk_funcs = …; static const struct intel_cdclk_funcs gm45_cdclk_funcs = …; /* G45 uses G33 */ static const struct intel_cdclk_funcs i965gm_cdclk_funcs = …; /* i965G uses fixed 400 */ static const struct intel_cdclk_funcs pnv_cdclk_funcs = …; static const struct intel_cdclk_funcs g33_cdclk_funcs = …; static const struct intel_cdclk_funcs i945gm_cdclk_funcs = …; /* i945G uses fixed 400 */ static const struct intel_cdclk_funcs i915gm_cdclk_funcs = …; static const struct intel_cdclk_funcs i915g_cdclk_funcs = …; static const struct intel_cdclk_funcs i865g_cdclk_funcs = …; static const struct intel_cdclk_funcs i85x_cdclk_funcs = …; static const struct intel_cdclk_funcs i845g_cdclk_funcs = …; static const struct intel_cdclk_funcs i830_cdclk_funcs = …; /** * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks * @dev_priv: i915 device */ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) { … }
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