linux/drivers/phy/st/phy-stm32-usbphyc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * STMicroelectronics STM32 USB PHY Controller driver
 *
 * Copyright (C) 2018 STMicroelectronics
 * Author(s): Amelie Delaunay <[email protected]>.
 */
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/units.h>

#define STM32_USBPHYC_PLL
#define STM32_USBPHYC_MISC
#define STM32_USBPHYC_MONITOR(X)
#define STM32_USBPHYC_TUNE(X)
#define STM32_USBPHYC_VERSION

/* STM32_USBPHYC_PLL bit fields */
#define PLLNDIV
#define PLLFRACIN
#define PLLEN
#define PLLSTRB
#define PLLSTRBYP
#define PLLFRACCTL
#define PLLDITHEN0
#define PLLDITHEN1

/* STM32_USBPHYC_MISC bit fields */
#define SWITHOST

/* STM32_USBPHYC_MONITOR bit fields */
#define STM32_USBPHYC_MON_OUT
#define STM32_USBPHYC_MON_SEL
#define STM32_USBPHYC_MON_SEL_LOCKP
#define STM32_USBPHYC_MON_OUT_LOCKP

/* STM32_USBPHYC_TUNE bit fields */
#define INCURREN
#define INCURRINT
#define LFSCAPEN
#define HSDRVSLEW
#define HSDRVDCCUR
#define HSDRVDCLEV
#define HSDRVCURINCR
#define FSDRVRFADJ
#define HSDRVRFRED
#define HSDRVCHKITRM
#define HSDRVCHKZTRM
#define OTPCOMP
#define SQLCHCTL
#define HDRXGNEQEN
#define HSRXOFF
#define HSFALLPREEM
#define SHTCCTCTLPROT
#define STAGSEL

enum boosting_vals {};

enum dc_level_vals {};

enum current_trim {};

enum impedance_trim {};

enum squelch_level {};

enum rx_offset {};

/* STM32_USBPHYC_VERSION bit fields */
#define MINREV
#define MAJREV

#define PLL_FVCO_MHZ
#define PLL_INFF_MIN_RATE_HZ
#define PLL_INFF_MAX_RATE_HZ

struct pll_params {};

struct stm32_usbphyc_phy {};

struct stm32_usbphyc {};

static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
{}

static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
{}

static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
{}

static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
{}

static void stm32_usbphyc_get_pll_params(u32 clk_rate,
					 struct pll_params *pll_params)
{}

static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
{}

static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
{}

static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
{}

static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
{}

static int stm32_usbphyc_phy_init(struct phy *phy)
{}

static int stm32_usbphyc_phy_exit(struct phy *phy)
{}

static int stm32_usbphyc_phy_power_on(struct phy *phy)
{}

static int stm32_usbphyc_phy_power_off(struct phy *phy)
{}

static const struct phy_ops stm32_usbphyc_phy_ops =;

static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
{}

static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
{}

static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{}

static const struct clk_ops usbphyc_clk48_ops =;

static void stm32_usbphyc_clk48_unregister(void *data)
{}

static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
{}

static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
				     struct device_node *np, u32 index)
{}

static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
				       u32 utmi_switch)
{}

static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
					  const struct of_phandle_args *args)
{}

static int stm32_usbphyc_probe(struct platform_device *pdev)
{}

static void stm32_usbphyc_remove(struct platform_device *pdev)
{}

static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
{}

static SIMPLE_DEV_PM_OPS(stm32_usbphyc_pm_ops, NULL, stm32_usbphyc_resume);

static const struct of_device_id stm32_usbphyc_of_match[] =;
MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);

static struct platform_driver stm32_usbphyc_driver =;
module_platform_driver();

MODULE_DESCRIPTION();
MODULE_AUTHOR();
MODULE_LICENSE();