/* * Copyright © 2016 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * */ #include "i9xx_plane_regs.h" #include "intel_color.h" #include "intel_color_regs.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" struct intel_color_funcs { … }; #define CTM_COEFF_SIGN … #define CTM_COEFF_1_0 … #define CTM_COEFF_2_0 … #define CTM_COEFF_4_0 … #define CTM_COEFF_8_0 … #define CTM_COEFF_0_5 … #define CTM_COEFF_0_25 … #define CTM_COEFF_0_125 … #define CTM_COEFF_LIMITED_RANGE … #define CTM_COEFF_NEGATIVE(coeff) … #define CTM_COEFF_ABS(coeff) … #define LEGACY_LUT_LENGTH … /* * ILK+ csc matrix: * * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0| * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1| * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2| * * ILK/SNB don't have explicit post offsets, and instead * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used: * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16 */ /* * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point * format). This macro takes the coefficient we want transformed and the * number of fractional bits. * * We only have a 9 bits precision window which slides depending on the value * of the CTM coefficient and we write the value from bit 3. We also round the * value. */ #define ILK_CSC_COEFF_FP(coeff, fbits) … #define ILK_CSC_COEFF_1_0 … #define ILK_CSC_COEFF_LIMITED_RANGE … #define ILK_CSC_POSTOFF_LIMITED_RANGE … static const struct intel_csc_matrix ilk_csc_matrix_identity = …; /* Full range RGB -> limited range RGB matrix */ static const struct intel_csc_matrix ilk_csc_matrix_limited_range = …; /* BT.709 full range RGB -> limited range YCbCr matrix */ static const struct intel_csc_matrix ilk_csc_matrix_rgb_to_ycbcr = …; static void intel_csc_clear(struct intel_csc_matrix *csc) { … } static bool lut_is_legacy(const struct drm_property_blob *lut) { … } /* * When using limited range, multiply the matrix given by userspace by * the matrix that we would use for the limited range. */ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input) { … } static void ilk_update_pipe_csc(struct intel_crtc *crtc, const struct intel_csc_matrix *csc) { … } static void ilk_read_pipe_csc(struct intel_crtc *crtc, struct intel_csc_matrix *csc) { … } static void ilk_read_csc(struct intel_crtc_state *crtc_state) { … } static void skl_read_csc(struct intel_crtc_state *crtc_state) { … } static void icl_update_output_csc(struct intel_crtc *crtc, const struct intel_csc_matrix *csc) { … } static void icl_read_output_csc(struct intel_crtc *crtc, struct intel_csc_matrix *csc) { … } static void icl_read_csc(struct intel_crtc_state *crtc_state) { … } static bool ilk_limited_range(const struct intel_crtc_state *crtc_state) { … } static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state) { … } static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) { … } static void ilk_csc_copy(struct drm_i915_private *i915, struct intel_csc_matrix *dst, const struct intel_csc_matrix *src) { … } static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, struct intel_csc_matrix *csc, bool limited_color_range) { … } static void ilk_assign_csc(struct intel_crtc_state *crtc_state) { … } static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) { … } static void icl_assign_csc(struct intel_crtc_state *crtc_state) { … } static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) { … } static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits) { … } /* * VLV/CHV Wide Gamut Color Correction (WGC) CSC * |r| | c0 c1 c2 | |r| * |g| = | c3 c4 c5 | x |g| * |b| | c6 c7 c8 | |b| * * Coefficients are two's complement s2.10. */ static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state, struct intel_csc_matrix *csc) { … } static void vlv_load_wgc_csc(struct intel_crtc *crtc, const struct intel_csc_matrix *csc) { … } static void vlv_read_wgc_csc(struct intel_crtc *crtc, struct intel_csc_matrix *csc) { … } static void vlv_read_csc(struct intel_crtc_state *crtc_state) { … } static void vlv_assign_csc(struct intel_crtc_state *crtc_state) { … } /* * CHV Color Gamut Mapping (CGM) CSC * |r| | c0 c1 c2 | |r| * |g| = | c3 c4 c5 | x |g| * |b| | c6 c7 c8 | |b| * * Coefficients are two's complement s4.12. */ static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state, struct intel_csc_matrix *csc) { … } #define CHV_CGM_CSC_COEFF_1_0 … static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = …; static void chv_load_cgm_csc(struct intel_crtc *crtc, const struct intel_csc_matrix *csc) { … } static void chv_read_cgm_csc(struct intel_crtc *crtc, struct intel_csc_matrix *csc) { … } static void chv_read_csc(struct intel_crtc_state *crtc_state) { … } static void chv_assign_csc(struct intel_crtc_state *crtc_state) { … } /* convert hw value with given bit_precision to lut property val */ static u32 intel_color_lut_pack(u32 val, int bit_precision) { … } static u32 i9xx_lut_8(const struct drm_color_lut *color) { … } static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) { … } /* i8xx/i9xx+ 10bit slope format "even DW" (low 8 bits) */ static u32 _i9xx_lut_10_ldw(u16 a) { … } static u32 i9xx_lut_10_ldw(const struct drm_color_lut *color) { … } /* i8xx/i9xx+ 10bit slope format "odd DW" (high 2 bits + slope) */ static u32 _i9xx_lut_10_udw(u16 a, u16 b) { … } static u32 i9xx_lut_10_udw(const struct drm_color_lut *color) { … } static void i9xx_lut_10_pack(struct drm_color_lut *color, u32 ldw, u32 udw) { … } static void i9xx_lut_10_pack_slope(struct drm_color_lut *color, u32 ldw, u32 udw) { … } /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) { … } /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) { … } static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) { … } static u16 i965_lut_11p6_max_pack(u32 val) { … } static u32 ilk_lut_10(const struct drm_color_lut *color) { … } static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) { … } /* ilk+ "12.4" interpolated format (low 6 bits) */ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) { … } /* ilk+ "12.4" interpolated format (high 10 bits) */ static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) { … } static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) { … } static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state) { … } static void skl_color_commit_noarm(const struct intel_crtc_state *crtc_state) { … } static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state) { … } static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state) { … } static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state) { … } static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state) { … } static u32 hsw_read_gamma_mode(struct intel_crtc *crtc) { … } static u32 ilk_read_csc_mode(struct intel_crtc *crtc) { … } static void i9xx_get_config(struct intel_crtc_state *crtc_state) { … } static void hsw_get_config(struct intel_crtc_state *crtc_state) { … } static void skl_get_config(struct intel_crtc_state *crtc_state) { … } static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state) { … } static void icl_color_commit_arm(const struct intel_crtc_state *crtc_state) { … } static void icl_color_post_update(const struct intel_crtc_state *crtc_state) { … } static struct drm_property_blob * create_linear_lut(struct drm_i915_private *i915, int lut_size) { … } static u16 lut_limited_range(unsigned int value) { … } static struct drm_property_blob * create_resized_lut(struct drm_i915_private *i915, const struct drm_property_blob *blob_in, int lut_out_size, bool limited_color_range) { … } static void i9xx_load_lut_8(struct intel_crtc *crtc, const struct drm_property_blob *blob) { … } static void i9xx_load_lut_10(struct intel_crtc *crtc, const struct drm_property_blob *blob) { … } static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) { … } static void i965_load_lut_10p6(struct intel_crtc *crtc, const struct drm_property_blob *blob) { … } static void i965_load_luts(const struct intel_crtc_state *crtc_state) { … } static void ilk_lut_write(const struct intel_crtc_state *crtc_state, i915_reg_t reg, u32 val) { … } static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob) { … } static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob) { … } static void ilk_load_luts(const struct intel_crtc_state *crtc_state) { … } static int ivb_lut_10_size(u32 prec_index) { … } /* * IVB/HSW Bspec / PAL_PREC_INDEX: * "Restriction : Index auto increment mode is not * supported and must not be enabled." */ static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob, u32 prec_index) { … } /* On BDW+ the index auto increment mode actually works */ static void bdw_load_lut_10(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob, u32 prec_index) { … } static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) { … } static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state) { … } static void ivb_load_luts(const struct intel_crtc_state *crtc_state) { … } static void bdw_load_luts(const struct intel_crtc_state *crtc_state) { … } static int glk_degamma_lut_size(struct drm_i915_private *i915) { … } static u32 glk_degamma_lut(const struct drm_color_lut *color) { … } static void glk_degamma_lut_pack(struct drm_color_lut *entry, u32 val) { … } static u32 mtl_degamma_lut(const struct drm_color_lut *color) { … } static void mtl_degamma_lut_pack(struct drm_color_lut *entry, u32 val) { … } static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob) { … } static void glk_load_luts(const struct intel_crtc_state *crtc_state) { … } static void ivb_load_lut_max(const struct intel_crtc_state *crtc_state, const struct drm_color_lut *color) { … } static void icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) { … } static void icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) { … } static void icl_load_luts(const struct intel_crtc_state *crtc_state) { … } static void vlv_load_luts(const struct intel_crtc_state *crtc_state) { … } static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) { … } static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) { … } static void chv_cgm_degamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) { … } static void chv_load_cgm_degamma(struct intel_crtc *crtc, const struct drm_property_blob *blob) { … } static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) { … } static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) { … } static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) { … } static void chv_load_cgm_gamma(struct intel_crtc *crtc, const struct drm_property_blob *blob) { … } static void chv_load_luts(const struct intel_crtc_state *crtc_state) { … } void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { … } void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state) { … } void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) { … } void intel_color_post_update(const struct intel_crtc_state *crtc_state) { … } void intel_color_prepare_commit(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) { … } void intel_color_wait_commit(const struct intel_crtc_state *crtc_state) { … } bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) { … } static bool intel_can_preload_luts(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool vlv_can_preload_luts(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool chv_can_preload_luts(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } int intel_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } void intel_color_get_config(struct intel_crtc_state *crtc_state) { … } bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool need_plane_update(struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { … } static int intel_color_add_affected_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state) { … } static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state) { … } static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state) { … } static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state) { … } static int check_lut_size(struct drm_i915_private *i915, const struct drm_property_blob *lut, int expected) { … } static int _check_luts(const struct intel_crtc_state *crtc_state, u32 degamma_tests, u32 gamma_tests) { … } static int check_luts(const struct intel_crtc_state *crtc_state) { … } static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) { … } static int i9xx_lut_10_diff(u16 a, u16 b) { … } static int i9xx_check_lut_10(struct drm_i915_private *dev_priv, const struct drm_property_blob *blob) { … } void intel_color_assert_luts(const struct intel_crtc_state *crtc_state) { … } static void intel_assign_luts(struct intel_crtc_state *crtc_state) { … } static int i9xx_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } /* * VLV color pipeline: * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 */ static int vlv_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) { … } /* * CHV color pipeline: * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma -> * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 * * We always bypass the WGC csc and use the CGM csc * instead since it has degamma and better precision. */ static int chv_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state) { … } static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state) { … } static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) { … } static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) { … } static int ilk_assign_luts(struct intel_crtc_state *crtc_state) { … } static int ilk_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) { … } static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) { … } static int ivb_assign_luts(struct intel_crtc_state *crtc_state) { … } static int ivb_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) { … } static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state) { … } static int glk_assign_luts(struct intel_crtc_state *crtc_state) { … } static int glk_check_luts(const struct intel_crtc_state *crtc_state) { … } static int glk_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) { … } static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) { … } static int icl_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int i9xx_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int i965_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int ilk_gamma_mode_precision(u32 gamma_mode) { … } static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state) { … } static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state) { … } static int ilk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int ilk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int ivb_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int ivb_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int chv_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int chv_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int glk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int glk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state) { … } static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state) { … } static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { … } static bool err_check(const struct drm_color_lut *lut1, const struct drm_color_lut *lut2, u32 err) { … } static bool intel_lut_entries_equal(const struct drm_color_lut *lut1, const struct drm_color_lut *lut2, int lut_size, u32 err) { … } static bool intel_lut_equal(const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, int check_size, int precision) { … } static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool i965_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool chv_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool glk_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static bool icl_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob1, const struct drm_property_blob *blob2, bool is_pre_csc_lut) { … } static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) { … } static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc) { … } static void i9xx_read_luts(struct intel_crtc_state *crtc_state) { … } static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) { … } static void i965_read_luts(struct intel_crtc_state *crtc_state) { … } static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc) { … } static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) { … } static void chv_get_config(struct intel_crtc_state *crtc_state) { … } static void chv_read_luts(struct intel_crtc_state *crtc_state) { … } static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) { … } static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) { … } static void ilk_get_config(struct intel_crtc_state *crtc_state) { … } static void ilk_read_luts(struct intel_crtc_state *crtc_state) { … } /* * IVB/HSW Bspec / PAL_PREC_INDEX: * "Restriction : Index auto increment mode is not * supported and must not be enabled." */ static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc, u32 prec_index) { … } static void ivb_read_luts(struct intel_crtc_state *crtc_state) { … } /* On BDW+ the index auto increment mode actually works */ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, u32 prec_index) { … } static void bdw_read_luts(struct intel_crtc_state *crtc_state) { … } static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc) { … } static void glk_read_luts(struct intel_crtc_state *crtc_state) { … } static struct drm_property_blob * icl_read_lut_multi_segment(struct intel_crtc *crtc) { … } static void icl_read_luts(struct intel_crtc_state *crtc_state) { … } static const struct intel_color_funcs chv_color_funcs = …; static const struct intel_color_funcs vlv_color_funcs = …; static const struct intel_color_funcs i965_color_funcs = …; static const struct intel_color_funcs i9xx_color_funcs = …; static const struct intel_color_funcs tgl_color_funcs = …; static const struct intel_color_funcs icl_color_funcs = …; static const struct intel_color_funcs glk_color_funcs = …; static const struct intel_color_funcs skl_color_funcs = …; static const struct intel_color_funcs bdw_color_funcs = …; static const struct intel_color_funcs hsw_color_funcs = …; static const struct intel_color_funcs ivb_color_funcs = …; static const struct intel_color_funcs ilk_color_funcs = …; void intel_color_crtc_init(struct intel_crtc *crtc) { … } int intel_color_init(struct drm_i915_private *i915) { … } void intel_color_init_hooks(struct drm_i915_private *i915) { … }
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