/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_FDI_REGS_H__ #define __INTEL_FDI_REGS_H__ #include "intel_display_reg_defs.h" #define FDI_PLL_BIOS_0 … #define FDI_PLL_FB_CLOCK_MASK … #define FDI_PLL_BIOS_1 … #define FDI_PLL_BIOS_2 … #define DISPLAY_PORT_PLL_BIOS_0 … #define DISPLAY_PORT_PLL_BIOS_1 … #define DISPLAY_PORT_PLL_BIOS_2 … #define FDI_PLL_FREQ_CTL … #define FDI_PLL_FREQ_CHANGE_REQUEST … #define FDI_PLL_FREQ_LOCK_LIMIT_MASK … #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK … #define _FDI_RXA_CHICKEN … #define _FDI_RXB_CHICKEN … #define FDI_RX_PHASE_SYNC_POINTER_OVR … #define FDI_RX_PHASE_SYNC_POINTER_EN … #define FDI_RX_CHICKEN(pipe) … /* CPU: FDI_TX */ #define _FDI_TXA_CTL … #define _FDI_TXB_CTL … #define FDI_TX_CTL(pipe) … #define FDI_TX_DISABLE … #define FDI_TX_ENABLE … #define FDI_LINK_TRAIN_PATTERN_1 … #define FDI_LINK_TRAIN_PATTERN_2 … #define FDI_LINK_TRAIN_PATTERN_IDLE … #define FDI_LINK_TRAIN_NONE … #define FDI_LINK_TRAIN_VOLTAGE_0_4V … #define FDI_LINK_TRAIN_VOLTAGE_0_6V … #define FDI_LINK_TRAIN_VOLTAGE_0_8V … #define FDI_LINK_TRAIN_VOLTAGE_1_2V … #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE … #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X … #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X … #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X … /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. SNB has different settings. */ /* SNB A-stepping */ #define FDI_LINK_TRAIN_400MV_0DB_SNB_A … #define FDI_LINK_TRAIN_400MV_6DB_SNB_A … #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A … #define FDI_LINK_TRAIN_800MV_0DB_SNB_A … /* SNB B-stepping */ #define FDI_LINK_TRAIN_400MV_0DB_SNB_B … #define FDI_LINK_TRAIN_400MV_6DB_SNB_B … #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B … #define FDI_LINK_TRAIN_800MV_0DB_SNB_B … #define FDI_LINK_TRAIN_VOL_EMP_MASK … #define FDI_DP_PORT_WIDTH_SHIFT … #define FDI_DP_PORT_WIDTH_MASK … #define FDI_DP_PORT_WIDTH(width) … #define FDI_TX_ENHANCE_FRAME_ENABLE … /* Ironlake: hardwired to 1 */ #define FDI_TX_PLL_ENABLE … /* Ivybridge has different bits for lolz */ #define FDI_LINK_TRAIN_PATTERN_1_IVB … #define FDI_LINK_TRAIN_PATTERN_2_IVB … #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB … #define FDI_LINK_TRAIN_NONE_IVB … /* both Tx and Rx */ #define FDI_COMPOSITE_SYNC … #define FDI_LINK_TRAIN_AUTO … #define FDI_SCRAMBLING_ENABLE … #define FDI_SCRAMBLING_DISABLE … /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ #define _FDI_RXA_CTL … #define _FDI_RXB_CTL … #define FDI_RX_CTL(pipe) … #define FDI_RX_ENABLE … /* train, dp width same as FDI_TX */ #define FDI_FS_ERRC_ENABLE … #define FDI_FE_ERRC_ENABLE … #define FDI_RX_POLARITY_REVERSED_LPT … #define FDI_8BPC … #define FDI_10BPC … #define FDI_6BPC … #define FDI_12BPC … #define FDI_RX_LINK_REVERSAL_OVERRIDE … #define FDI_DMI_LINK_REVERSE_MASK … #define FDI_RX_PLL_ENABLE … #define FDI_FS_ERR_CORRECT_ENABLE … #define FDI_FE_ERR_CORRECT_ENABLE … #define FDI_FS_ERR_REPORT_ENABLE … #define FDI_FE_ERR_REPORT_ENABLE … #define FDI_RX_ENHANCE_FRAME_ENABLE … #define FDI_PCDCLK … /* CPT */ #define FDI_AUTO_TRAINING … #define FDI_LINK_TRAIN_PATTERN_1_CPT … #define FDI_LINK_TRAIN_PATTERN_2_CPT … #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT … #define FDI_LINK_TRAIN_NORMAL_CPT … #define FDI_LINK_TRAIN_PATTERN_MASK_CPT … #define _FDI_RXA_MISC … #define _FDI_RXB_MISC … #define FDI_RX_PWRDN_LANE1_MASK … #define FDI_RX_PWRDN_LANE1_VAL(x) … #define FDI_RX_PWRDN_LANE0_MASK … #define FDI_RX_PWRDN_LANE0_VAL(x) … #define FDI_RX_TP1_TO_TP2_48 … #define FDI_RX_TP1_TO_TP2_64 … #define FDI_RX_FDI_DELAY_90 … #define FDI_RX_MISC(pipe) … #define _FDI_RXA_TUSIZE1 … #define _FDI_RXA_TUSIZE2 … #define _FDI_RXB_TUSIZE1 … #define _FDI_RXB_TUSIZE2 … #define FDI_RX_TUSIZE1(pipe) … #define FDI_RX_TUSIZE2(pipe) … /* FDI_RX interrupt register format */ #define FDI_RX_INTER_LANE_ALIGN … #define FDI_RX_SYMBOL_LOCK … #define FDI_RX_BIT_LOCK … #define FDI_RX_TRAIN_PATTERN_2_FAIL … #define FDI_RX_FS_CODE_ERR … #define FDI_RX_FE_CODE_ERR … #define FDI_RX_SYMBOL_ERR_RATE_ABOVE … #define FDI_RX_HDCP_LINK_FAIL … #define FDI_RX_PIXEL_FIFO_OVERFLOW … #define FDI_RX_CROSS_CLOCK_OVERFLOW … #define FDI_RX_SYMBOL_QUEUE_OVERFLOW … #define _FDI_RXA_IIR … #define _FDI_RXA_IMR … #define _FDI_RXB_IIR … #define _FDI_RXB_IMR … #define FDI_RX_IIR(pipe) … #define FDI_RX_IMR(pipe) … #define FDI_PLL_CTL_1 … #define FDI_PLL_CTL_2 … #endif /* __INTEL_FDI_REGS_H__ */
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