/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_BACKLIGHT_REGS_H__ #define __INTEL_BACKLIGHT_REGS_H__ #include "intel_display_reg_defs.h" #define _VLV_BLC_PWM_CTL2_A … #define _VLV_BLC_PWM_CTL2_B … #define VLV_BLC_PWM_CTL2(pipe) … #define _VLV_BLC_PWM_CTL_A … #define _VLV_BLC_PWM_CTL_B … #define VLV_BLC_PWM_CTL(pipe) … #define _VLV_BLC_HIST_CTL_A … #define _VLV_BLC_HIST_CTL_B … #define VLV_BLC_HIST_CTL(pipe) … /* Backlight control */ #define BLC_PWM_CTL2 … #define BLM_PWM_ENABLE … #define BLM_COMBINATION_MODE … #define BLM_PIPE_SELECT … #define BLM_PIPE_SELECT_IVB … #define BLM_PIPE_A … #define BLM_PIPE_B … #define BLM_PIPE_C … #define BLM_TRANSCODER_A … #define BLM_TRANSCODER_B … #define BLM_TRANSCODER_C … #define BLM_TRANSCODER_EDP … #define BLM_PIPE(pipe) … #define BLM_POLARITY_I965 … #define BLM_PHASE_IN_INTERUPT_STATUS … #define BLM_PHASE_IN_ENABLE … #define BLM_PHASE_IN_INTERUPT_ENABL … #define BLM_PHASE_IN_TIME_BASE_SHIFT … #define BLM_PHASE_IN_TIME_BASE_MASK … #define BLM_PHASE_IN_COUNT_SHIFT … #define BLM_PHASE_IN_COUNT_MASK … #define BLM_PHASE_IN_INCR_SHIFT … #define BLM_PHASE_IN_INCR_MASK … #define BLC_PWM_CTL … /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * * The actual value is this field multiplied by two. */ #define BACKLIGHT_MODULATION_FREQ_SHIFT … #define BACKLIGHT_MODULATION_FREQ_MASK … #define BLM_LEGACY_MODE … /* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. * * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. */ #define BACKLIGHT_DUTY_CYCLE_SHIFT … #define BACKLIGHT_DUTY_CYCLE_MASK … #define BACKLIGHT_DUTY_CYCLE_MASK_PNV … #define BLM_POLARITY_PNV … #define BLC_HIST_CTL … #define BLM_HISTOGRAM_ENABLE … /* New registers for PCH-split platforms. Safe where new bits show up, the * register layout machtes with gen4 BLC_PWM_CTL[12]. */ #define BLC_PWM_CPU_CTL2 … #define BLC_PWM_CPU_CTL … #define HSW_BLC_PWM2_CTL … /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ #define BLC_PWM_PCH_CTL1 … #define BLM_PCH_PWM_ENABLE … #define BLM_PCH_OVERRIDE_ENABLE … #define BLM_PCH_POLARITY … #define BLC_PWM_PCH_CTL2 … /* BXT backlight register definition. */ #define _BXT_BLC_PWM_CTL1 … #define BXT_BLC_PWM_ENABLE … #define BXT_BLC_PWM_POLARITY … #define _BXT_BLC_PWM_FREQ1 … #define _BXT_BLC_PWM_DUTY1 … #define _BXT_BLC_PWM_CTL2 … #define _BXT_BLC_PWM_FREQ2 … #define _BXT_BLC_PWM_DUTY2 … #define BXT_BLC_PWM_CTL(controller) … #define BXT_BLC_PWM_FREQ(controller) … #define BXT_BLC_PWM_DUTY(controller) … /* Utility pin */ #define UTIL_PIN_CTL … #define UTIL_PIN_ENABLE … #define UTIL_PIN_PIPE_MASK … #define UTIL_PIN_PIPE(x) … #define UTIL_PIN_MODE_MASK … #define UTIL_PIN_MODE_DATA … #define UTIL_PIN_MODE_PWM … #define UTIL_PIN_MODE_VBLANK … #define UTIL_PIN_MODE_VSYNC … #define UTIL_PIN_MODE_EYE_LEVEL … #define UTIL_PIN_OUTPUT_DATA … #define UTIL_PIN_POLARITY … #define UTIL_PIN_DIRECTION_INPUT … #define UTIL_PIN_INPUT_DATA … #endif /* __INTEL_BACKLIGHT_REGS_H__ */
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