/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_DKL_PHY_REGS__ #define __INTEL_DKL_PHY_REGS__ #include <linux/types.h> struct intel_dkl_phy_reg { … }; #define _DKL_PHY1_BASE … #define _DKL_PHY2_BASE … #define _DKL_PHY3_BASE … #define _DKL_PHY4_BASE … #define _DKL_PHY5_BASE … #define _DKL_PHY6_BASE … #define DKL_REG_TC_PORT(__reg) … /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ #define DKL_REG_MMIO(__reg) … #define _DKL_REG_PHY_BASE(tc_port) … #define _DKL_BANK_SHIFT … #define _DKL_REG_BANK_OFFSET(phy_offset) … #define _DKL_REG_BANK_IDX(phy_offset) … #define _DKL_REG(tc_port, phy_offset) … #define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) … #define _DKL_PCS_DW5_LN0 … #define _DKL_PCS_DW5_LN1 … #define DKL_PCS_DW5(tc_port, ln) … #define DKL_PCS_DW5_CORE_SOFTRESET … #define _DKL_PLL_DIV0 … #define DKL_PLL_DIV0(tc_port) … #define DKL_PLL_DIV0_AFC_STARTUP_MASK … #define DKL_PLL_DIV0_AFC_STARTUP(val) … #define DKL_PLL_DIV0_INTEG_COEFF(x) … #define DKL_PLL_DIV0_INTEG_COEFF_MASK … #define DKL_PLL_DIV0_PROP_COEFF(x) … #define DKL_PLL_DIV0_PROP_COEFF_MASK … #define DKL_PLL_DIV0_FBPREDIV_SHIFT … #define DKL_PLL_DIV0_FBPREDIV(x) … #define DKL_PLL_DIV0_FBPREDIV_MASK … #define DKL_PLL_DIV0_FBDIV_INT(x) … #define DKL_PLL_DIV0_FBDIV_INT_MASK … #define DKL_PLL_DIV0_MASK … #define _DKL_PLL_DIV1 … #define DKL_PLL_DIV1(tc_port) … #define DKL_PLL_DIV1_IREF_TRIM(x) … #define DKL_PLL_DIV1_IREF_TRIM_MASK … #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) … #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK … #define _DKL_PLL_SSC … #define DKL_PLL_SSC(tc_port) … #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) … #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK … #define DKL_PLL_SSC_STEP_LEN(x) … #define DKL_PLL_SSC_STEP_LEN_MASK … #define DKL_PLL_SSC_STEP_NUM(x) … #define DKL_PLL_SSC_STEP_NUM_MASK … #define DKL_PLL_SSC_EN … #define _DKL_PLL_BIAS … #define DKL_PLL_BIAS(tc_port) … #define DKL_PLL_BIAS_FRAC_EN_H … #define DKL_PLL_BIAS_FBDIV_SHIFT … #define DKL_PLL_BIAS_FBDIV_FRAC(x) … #define DKL_PLL_BIAS_FBDIV_FRAC_MASK … #define _DKL_PLL_TDC_COLDST_BIAS … #define DKL_PLL_TDC_COLDST_BIAS(tc_port) … #define DKL_PLL_TDC_SSC_STEP_SIZE(x) … #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK … #define DKL_PLL_TDC_FEED_FWD_GAIN(x) … #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK … #define _DKL_REFCLKIN_CTL … #define DKL_REFCLKIN_CTL(tc_port) … /* Bits are the same as MG_REFCLKIN_CTL */ #define _DKL_CLKTOP2_HSCLKCTL … #define DKL_CLKTOP2_HSCLKCTL(rc_port) … /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ #define _DKL_CLKTOP2_CORECLKCTL1 … #define DKL_CLKTOP2_CORECLKCTL1(tc_port) … /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ #define _DKL_TX_DPCNTL0_LN0 … #define _DKL_TX_DPCNTL0_LN1 … #define DKL_TX_DPCNTL0(tc_port, ln) … #define DKL_TX_PRESHOOT_COEFF(x) … #define DKL_TX_PRESHOOT_COEFF_MASK … #define DKL_TX_DE_EMPHASIS_COEFF(x) … #define DKL_TX_DE_EMPAHSIS_COEFF_MASK … #define DKL_TX_VSWING_CONTROL(x) … #define DKL_TX_VSWING_CONTROL_MASK … #define _DKL_TX_DPCNTL1_LN0 … #define _DKL_TX_DPCNTL1_LN1 … #define DKL_TX_DPCNTL1(tc_port, ln) … /* Bits are the same as DKL_TX_DPCNTRL0 */ #define _DKL_TX_DPCNTL2_LN0 … #define _DKL_TX_DPCNTL2_LN1 … #define DKL_TX_DPCNTL2(tc_port, ln) … #define DKL_TX_DP20BITMODE … #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK … #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) … #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK … #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) … #define _DKL_TX_FW_CALIB_LN0 … #define _DKL_TX_FW_CALIB_LN1 … #define DKL_TX_FW_CALIB(tc_port, ln) … #define DKL_TX_CFG_DISABLE_WAIT_INIT … #define _DKL_TX_PMD_LANE_SUS_LN0 … #define _DKL_TX_PMD_LANE_SUS_LN1 … #define DKL_TX_PMD_LANE_SUS(tc_port, ln) … #define _DKL_TX_DW17_LN0 … #define _DKL_TX_DW17_LN1 … #define DKL_TX_DW17(tc_port, ln) … #define _DKL_TX_DW18_LN0 … #define _DKL_TX_DW18_LN1 … #define DKL_TX_DW18(tc_port, ln) … #define _DKL_DP_MODE_LN0 … #define _DKL_DP_MODE_LN1 … #define DKL_DP_MODE(tc_port, ln) … #define _DKL_CMN_UC_DW27 … #define DKL_CMN_UC_DW_27(tc_port) … #define DKL_CMN_UC_DW27_UC_HEALTH … /* * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address * bits that point the 4KB window into the full PHY register space. */ #define _HIP_INDEX_REG0 … #define _HIP_INDEX_REG1 … #define HIP_INDEX_REG(tc_port) … #define _HIP_INDEX_SHIFT(tc_port) … #define HIP_INDEX_VAL(tc_port, val) … #endif /* __INTEL_DKL_PHY_REGS__ */
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