/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_LVDS_REGS_H__ #define __INTEL_LVDS_REGS_H__ #include "intel_display_reg_defs.h" /* LVDS port control */ #define LVDS … /* * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ #define LVDS_PORT_EN … /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPE_SEL_MASK … #define LVDS_PIPE_SEL(pipe) … #define LVDS_PIPE_SEL_MASK_CPT … #define LVDS_PIPE_SEL_CPT(pipe) … /* LVDS dithering flag on 965/g4x platform */ #define LVDS_ENABLE_DITHER … /* LVDS sync polarity flags. Set to invert (i.e. negative) */ #define LVDS_VSYNC_POLARITY … #define LVDS_HSYNC_POLARITY … /* Enable border for unscaled (or aspect-scaled) display */ #define LVDS_BORDER_ENABLE … /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ #define LVDS_A0A2_CLKA_POWER_MASK … #define LVDS_A0A2_CLKA_POWER_DOWN … #define LVDS_A0A2_CLKA_POWER_UP … /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ #define LVDS_A3_POWER_MASK … #define LVDS_A3_POWER_DOWN … #define LVDS_A3_POWER_UP … /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ #define LVDS_CLKB_POWER_MASK … #define LVDS_CLKB_POWER_DOWN … #define LVDS_CLKB_POWER_UP … /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ #define LVDS_B0B3_POWER_MASK … #define LVDS_B0B3_POWER_DOWN … #define LVDS_B0B3_POWER_UP … #define PCH_LVDS … #define LVDS_DETECTED … #endif /* __INTEL_LVDS_REGS_H__ */
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