/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_VDSC_REGS_H__ #define __INTEL_VDSC_REGS_H__ #include "intel_display_reg_defs.h" /* Display Stream Splitter Control */ #define DSS_CTL1 … #define SPLITTER_ENABLE … #define JOINER_ENABLE … #define DUAL_LINK_MODE_INTERLEAVE … #define DUAL_LINK_MODE_FRONTBACK … #define OVERLAP_PIXELS_MASK … #define OVERLAP_PIXELS(pixels) … #define LEFT_DL_BUF_TARGET_DEPTH_MASK … #define LEFT_DL_BUF_TARGET_DEPTH(pixels) … #define MAX_DL_BUFFER_TARGET_DEPTH … #define DSS_CTL2 … #define LEFT_BRANCH_VDSC_ENABLE … #define RIGHT_BRANCH_VDSC_ENABLE … #define RIGHT_DL_BUF_TARGET_DEPTH_MASK … #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) … #define _ICL_PIPE_DSS_CTL1_PB … #define _ICL_PIPE_DSS_CTL1_PC … #define ICL_PIPE_DSS_CTL1(pipe) … #define BIG_JOINER_ENABLE … #define PRIMARY_BIG_JOINER_ENABLE … #define VGA_CENTERING_ENABLE … #define SPLITTER_CONFIGURATION_MASK … #define SPLITTER_CONFIGURATION_2_SEGMENT … #define SPLITTER_CONFIGURATION_4_SEGMENT … #define UNCOMPRESSED_JOINER_PRIMARY … #define UNCOMPRESSED_JOINER_SECONDARY … #define _ICL_PIPE_DSS_CTL2_PB … #define _ICL_PIPE_DSS_CTL2_PC … #define ICL_PIPE_DSS_CTL2(pipe) … /* Icelake Display Stream Compression Registers */ #define DSCA_PICTURE_PARAMETER_SET_0 … #define DSCC_PICTURE_PARAMETER_SET_0 … #define _DSCA_PPS_0 … #define _DSCC_PPS_0 … #define DSCA_PPS(pps) … #define DSCC_PPS(pps) … #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB … #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB … #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC … #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC … #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) … #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) … #define _ICL_DSC0_PPS_0(pipe) … #define _ICL_DSC1_PPS_0(pipe) … #define ICL_DSC0_PPS(pipe, pps) … #define ICL_DSC1_PPS(pipe, pps) … /* PPS 0 */ #define DSC_PPS0_NATIVE_422_ENABLE … #define DSC_PPS0_NATIVE_420_ENABLE … #define DSC_PPS0_ALT_ICH_SEL … #define DSC_PPS0_VBR_ENABLE … #define DSC_PPS0_422_ENABLE … #define DSC_PPS0_COLOR_SPACE_CONVERSION … #define DSC_PPS0_BLOCK_PREDICTION … #define DSC_PPS0_LINE_BUF_DEPTH_MASK … #define DSC_PPS0_LINE_BUF_DEPTH(depth) … #define DSC_PPS0_BPC_MASK … #define DSC_PPS0_BPC(bpc) … #define DSC_PPS0_VER_MINOR_MASK … #define DSC_PPS0_VER_MINOR(minor) … #define DSC_PPS0_VER_MAJOR_MASK … #define DSC_PPS0_VER_MAJOR(major) … /* PPS 1 */ #define DSC_PPS1_BPP_MASK … #define DSC_PPS1_BPP(bpp) … /* PPS 2 */ #define DSC_PPS2_PIC_WIDTH_MASK … #define DSC_PPS2_PIC_HEIGHT_MASK … #define DSC_PPS2_PIC_WIDTH(pic_width) … #define DSC_PPS2_PIC_HEIGHT(pic_height) … /* PPS 3 */ #define DSC_PPS3_SLICE_WIDTH_MASK … #define DSC_PPS3_SLICE_HEIGHT_MASK … #define DSC_PPS3_SLICE_WIDTH(slice_width) … #define DSC_PPS3_SLICE_HEIGHT(slice_height) … /* PPS 4 */ #define DSC_PPS4_INITIAL_DEC_DELAY_MASK … #define DSC_PPS4_INITIAL_XMIT_DELAY_MASK … #define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) … #define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) … /* PPS 5 */ #define DSC_PPS5_SCALE_DEC_INT_MASK … #define DSC_PPS5_SCALE_INC_INT_MASK … #define DSC_PPS5_SCALE_DEC_INT(scale_dec) … #define DSC_PPS5_SCALE_INC_INT(scale_inc) … /* PPS 6 */ #define DSC_PPS6_FLATNESS_MAX_QP_MASK … #define DSC_PPS6_FLATNESS_MIN_QP_MASK … #define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK … #define DSC_PPS6_INITIAL_SCALE_VALUE_MASK … #define DSC_PPS6_FLATNESS_MAX_QP(max_qp) … #define DSC_PPS6_FLATNESS_MIN_QP(min_qp) … #define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) … #define DSC_PPS6_INITIAL_SCALE_VALUE(value) … /* PPS 7 */ #define DSC_PPS7_NFL_BPG_OFFSET_MASK … #define DSC_PPS7_SLICE_BPG_OFFSET_MASK … #define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) … #define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) … /* PPS 8 */ #define DSC_PPS8_INITIAL_OFFSET_MASK … #define DSC_PPS8_FINAL_OFFSET_MASK … #define DSC_PPS8_INITIAL_OFFSET(initial_offset) … #define DSC_PPS8_FINAL_OFFSET(final_offset) … /* PPS 9 */ #define DSC_PPS9_RC_EDGE_FACTOR_MASK … #define DSC_PPS9_RC_MODEL_SIZE_MASK … #define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) … #define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) … /* PPS 10 */ #define DSC_PPS10_RC_TGT_OFF_LOW_MASK … #define DSC_PPS10_RC_TGT_OFF_HIGH_MASK … #define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK … #define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK … #define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) … #define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) … #define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) … #define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) … /* PPS 16 */ #define DSC_PPS16_SLICE_ROW_PR_FRME_MASK … #define DSC_PPS16_SLICE_PER_LINE_MASK … #define DSC_PPS16_SLICE_CHUNK_SIZE_MASK … #define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) … #define DSC_PPS16_SLICE_PER_LINE(slice_per_line) … #define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) … /* PPS 17 (MTL+) */ #define DSC_PPS17_SL_BPG_OFFSET_MASK … #define DSC_PPS17_SL_BPG_OFFSET(offset) … /* PPS 18 (MTL+) */ #define DSC_PPS18_NSL_BPG_OFFSET_MASK … #define DSC_PPS18_SL_OFFSET_ADJ_MASK … #define DSC_PPS18_NSL_BPG_OFFSET(offset) … #define DSC_PPS18_SL_OFFSET_ADJ(offset) … /* Icelake Rate Control Buffer Threshold Registers */ #define DSCA_RC_BUF_THRESH_0 … #define DSCA_RC_BUF_THRESH_0_UDW … #define DSCC_RC_BUF_THRESH_0 … #define DSCC_RC_BUF_THRESH_0_UDW … #define _ICL_DSC0_RC_BUF_THRESH_0_PB … #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB … #define _ICL_DSC1_RC_BUF_THRESH_0_PB … #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB … #define _ICL_DSC0_RC_BUF_THRESH_0_PC … #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC … #define _ICL_DSC1_RC_BUF_THRESH_0_PC … #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC … #define ICL_DSC0_RC_BUF_THRESH_0(pipe) … #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) … #define ICL_DSC1_RC_BUF_THRESH_0(pipe) … #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) … #define DSCA_RC_BUF_THRESH_1 … #define DSCA_RC_BUF_THRESH_1_UDW … #define DSCC_RC_BUF_THRESH_1 … #define DSCC_RC_BUF_THRESH_1_UDW … #define _ICL_DSC0_RC_BUF_THRESH_1_PB … #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB … #define _ICL_DSC1_RC_BUF_THRESH_1_PB … #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB … #define _ICL_DSC0_RC_BUF_THRESH_1_PC … #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC … #define _ICL_DSC1_RC_BUF_THRESH_1_PC … #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC … #define ICL_DSC0_RC_BUF_THRESH_1(pipe) … #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) … #define ICL_DSC1_RC_BUF_THRESH_1(pipe) … #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) … /* Icelake DSC Rate Control Range Parameter Registers */ #define DSCA_RC_RANGE_PARAMETERS_0 … #define DSCA_RC_RANGE_PARAMETERS_0_UDW … #define DSCC_RC_RANGE_PARAMETERS_0 … #define DSCC_RC_RANGE_PARAMETERS_0_UDW … #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC … #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC … #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) … #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) … #define RC_BPG_OFFSET_SHIFT … #define RC_MAX_QP_SHIFT … #define RC_MIN_QP_SHIFT … #define DSCA_RC_RANGE_PARAMETERS_1 … #define DSCA_RC_RANGE_PARAMETERS_1_UDW … #define DSCC_RC_RANGE_PARAMETERS_1 … #define DSCC_RC_RANGE_PARAMETERS_1_UDW … #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC … #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC … #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) … #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) … #define DSCA_RC_RANGE_PARAMETERS_2 … #define DSCA_RC_RANGE_PARAMETERS_2_UDW … #define DSCC_RC_RANGE_PARAMETERS_2 … #define DSCC_RC_RANGE_PARAMETERS_2_UDW … #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC … #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC … #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) … #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) … #define DSCA_RC_RANGE_PARAMETERS_3 … #define DSCA_RC_RANGE_PARAMETERS_3_UDW … #define DSCC_RC_RANGE_PARAMETERS_3 … #define DSCC_RC_RANGE_PARAMETERS_3_UDW … #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB … #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB … #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC … #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC … #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC … #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) … #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) … #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) … #endif /* __INTEL_VDSC_REGS_H__ */
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