/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_PPS_REGS_H__ #define __INTEL_PPS_REGS_H__ #include "intel_display_conversion.h" #include "intel_display_reg_defs.h" /* Panel power sequencing */ #define PPS_BASE … #define VLV_PPS_BASE … #define PCH_PPS_BASE … #define _MMIO_PPS(dev_priv, pps_idx, reg) … #define _PP_STATUS … #define PP_STATUS(dev_priv, pps_idx) … #define PP_ON … /* * Indicates that all dependencies of the panel are on: * * - PLL enabled * - pipe enabled * - LVDS/DVOB/DVOC on */ #define PP_READY … #define PP_SEQUENCE_MASK … #define PP_SEQUENCE_NONE … #define PP_SEQUENCE_POWER_UP … #define PP_SEQUENCE_POWER_DOWN … #define PP_CYCLE_DELAY_ACTIVE … #define PP_SEQUENCE_STATE_MASK … #define PP_SEQUENCE_STATE_OFF_IDLE … #define PP_SEQUENCE_STATE_OFF_S0_1 … #define PP_SEQUENCE_STATE_OFF_S0_2 … #define PP_SEQUENCE_STATE_OFF_S0_3 … #define PP_SEQUENCE_STATE_ON_IDLE … #define PP_SEQUENCE_STATE_ON_S1_1 … #define PP_SEQUENCE_STATE_ON_S1_2 … #define PP_SEQUENCE_STATE_ON_S1_3 … #define PP_SEQUENCE_STATE_RESET … #define _PP_CONTROL … #define PP_CONTROL(dev_priv, pps_idx) … #define PANEL_UNLOCK_MASK … #define PANEL_UNLOCK_REGS … #define BXT_POWER_CYCLE_DELAY_MASK … #define EDP_FORCE_VDD … #define EDP_BLC_ENABLE … #define PANEL_POWER_RESET … #define PANEL_POWER_ON … #define _PP_ON_DELAYS … #define PP_ON_DELAYS(dev_priv, pps_idx) … #define PANEL_PORT_SELECT_MASK … #define PANEL_PORT_SELECT_LVDS … #define PANEL_PORT_SELECT_DPA … #define PANEL_PORT_SELECT_DPC … #define PANEL_PORT_SELECT_DPD … #define PANEL_PORT_SELECT_VLV(port) … #define PANEL_POWER_UP_DELAY_MASK … #define PANEL_LIGHT_ON_DELAY_MASK … #define _PP_OFF_DELAYS … #define PP_OFF_DELAYS(dev_priv, pps_idx) … #define PANEL_POWER_DOWN_DELAY_MASK … #define PANEL_LIGHT_OFF_DELAY_MASK … #define _PP_DIVISOR … #define PP_DIVISOR(dev_priv, pps_idx) … #define PP_REFERENCE_DIVIDER_MASK … #define PANEL_POWER_CYCLE_DELAY_MASK … #endif /* __INTEL_PPS_REGS_H__ */
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