/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ #ifndef __SKL_WATERMARK_REGS_H__ #define __SKL_WATERMARK_REGS_H__ #include "intel_display_reg_defs.h" #define _PIPEA_MBUS_DBOX_CTL … #define _PIPEB_MBUS_DBOX_CTL … #define PIPE_MBUS_DBOX_CTL(pipe) … #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK … #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) … #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK … #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) … #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN … #define MBUS_DBOX_BW_CREDIT_MASK … #define MBUS_DBOX_BW_CREDIT(x) … #define MBUS_DBOX_BW_4CREDITS_MTL … #define MBUS_DBOX_BW_8CREDITS_MTL … #define MBUS_DBOX_B_CREDIT_MASK … #define MBUS_DBOX_B_CREDIT(x) … #define MBUS_DBOX_I_CREDIT_MASK … #define MBUS_DBOX_I_CREDIT(x) … #define MBUS_DBOX_A_CREDIT_MASK … #define MBUS_DBOX_A_CREDIT(x) … #define MBUS_UBOX_CTL … #define MBUS_BBOX_CTL_S1 … #define MBUS_BBOX_CTL_S2 … #define MBUS_CTL … #define MBUS_JOIN … #define MBUS_HASHING_MODE_MASK … #define MBUS_HASHING_MODE_2x2 … #define MBUS_HASHING_MODE_1x4 … #define MBUS_JOIN_PIPE_SELECT_MASK … #define MBUS_JOIN_PIPE_SELECT(pipe) … #define MBUS_JOIN_PIPE_SELECT_NONE … #define MBUS_TRANSLATION_THROTTLE_MIN_MASK … #define MBUS_TRANSLATION_THROTTLE_MIN(val) … /* * The below are numbered starting from "S1" on gen11/gen12, but starting * with display 13, the bspec switches to a 0-based numbering scheme * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). * We'll just use the 0-based numbering here for all platforms since it's the * way things will be named by the hardware team going forward, plus it's more * consistent with how most of the rest of our registers are named. */ #define _DBUF_CTL_S0 … #define _DBUF_CTL_S1 … #define _DBUF_CTL_S2 … #define _DBUF_CTL_S3 … #define DBUF_CTL_S(slice) … #define DBUF_POWER_REQUEST … #define DBUF_POWER_STATE … #define DBUF_TRACKER_STATE_SERVICE_MASK … #define DBUF_TRACKER_STATE_SERVICE(x) … #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK … #define DBUF_MIN_TRACKER_STATE_SERVICE(x) … #define MTL_LATENCY_LP0_LP1 … #define MTL_LATENCY_LP2_LP3 … #define MTL_LATENCY_LP4_LP5 … #define MTL_LATENCY_LEVEL_EVEN_MASK … #define MTL_LATENCY_LEVEL_ODD_MASK … #define MTL_LATENCY_SAGV … #define MTL_LATENCY_QCLK_SAGV … #define LNL_PKG_C_LATENCY … #define LNL_ADDED_WAKE_TIME_MASK … #define LNL_PKG_C_LATENCY_MASK … #endif /* __SKL_WATERMARK_REGS_H__ */
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