// SPDX-License-Identifier: GPL-2.0-or-later /* * phy-ti-pipe3 - PIPE3 PHY driver. * * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com * Author: Kishon Vijay Abraham I <[email protected]> */ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/slab.h> #include <linux/phy/phy.h> #include <linux/of.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> #include <linux/pm_runtime.h> #include <linux/delay.h> #include <linux/phy/omap_control_phy.h> #include <linux/of_platform.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #define PLL_STATUS … #define PLL_GO … #define PLL_CONFIGURATION1 … #define PLL_CONFIGURATION2 … #define PLL_CONFIGURATION3 … #define PLL_CONFIGURATION4 … #define PLL_REGM_MASK … #define PLL_REGM_SHIFT … #define PLL_REGM_F_MASK … #define PLL_REGM_F_SHIFT … #define PLL_REGN_MASK … #define PLL_REGN_SHIFT … #define PLL_SELFREQDCO_MASK … #define PLL_SELFREQDCO_SHIFT … #define PLL_SD_MASK … #define PLL_SD_SHIFT … #define SET_PLL_GO … #define PLL_LDOPWDN … #define PLL_TICOPWDN … #define PLL_LOCK … #define PLL_IDLE … #define SATA_PLL_SOFT_RESET … #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK … #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT … #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK … #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT … #define PIPE3_PHY_RX_POWERON … #define PIPE3_PHY_TX_POWERON … #define PCIE_PCS_MASK … #define PCIE_PCS_DELAY_COUNT_SHIFT … #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY … #define INTERFACE_MASK … #define INTERFACE_SHIFT … #define INTERFACE_MODE_USBSS … #define INTERFACE_MODE_SATA_1P5 … #define INTERFACE_MODE_SATA_3P0 … #define INTERFACE_MODE_PCIE … #define LOSD_MASK … #define LOSD_SHIFT … #define MEM_PLLDIV … #define PIPE3_PHY_RX_TRIM … #define MEM_DLL_TRIM_SEL_MASK … #define MEM_DLL_TRIM_SHIFT … #define PIPE3_PHY_RX_DLL … #define MEM_DLL_PHINT_RATE_MASK … #define MEM_DLL_PHINT_RATE_SHIFT … #define PIPE3_PHY_RX_DIGITAL_MODES … #define MEM_HS_RATE_MASK … #define MEM_HS_RATE_SHIFT … #define MEM_OVRD_HS_RATE … #define MEM_OVRD_HS_RATE_SHIFT … #define MEM_CDR_FASTLOCK … #define MEM_CDR_FASTLOCK_SHIFT … #define MEM_CDR_LBW_MASK … #define MEM_CDR_LBW_SHIFT … #define MEM_CDR_STEPCNT_MASK … #define MEM_CDR_STEPCNT_SHIFT … #define MEM_CDR_STL_MASK … #define MEM_CDR_STL_SHIFT … #define MEM_CDR_THR_MASK … #define MEM_CDR_THR_SHIFT … #define MEM_CDR_THR_MODE … #define MEM_CDR_THR_MODE_SHIFT … #define MEM_CDR_2NDO_SDM_MODE … #define MEM_CDR_2NDO_SDM_MODE_SHIFT … #define PIPE3_PHY_RX_EQUALIZER … #define MEM_EQLEV_MASK … #define MEM_EQLEV_SHIFT … #define MEM_EQFTC_MASK … #define MEM_EQFTC_SHIFT … #define MEM_EQCTL_MASK … #define MEM_EQCTL_SHIFT … #define MEM_OVRD_EQLEV … #define MEM_OVRD_EQLEV_SHIFT … #define MEM_OVRD_EQFTC … #define MEM_OVRD_EQFTC_SHIFT … #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES … #define MEM_CDR_LOS_SOURCE_MASK … #define MEM_CDR_LOS_SOURCE_SHIFT … /* * This is an Empirical value that works, need to confirm the actual * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status * to be correctly reflected in the PIPE3PHY_PLL_STATUS register. */ #define PLL_IDLE_TIME … #define PLL_LOCK_TIME … enum pipe3_mode { … }; struct pipe3_dpll_params { … }; struct pipe3_dpll_map { … }; struct pipe3_settings { … }; struct ti_pipe3 { … }; static struct pipe3_dpll_map dpll_map_usb[] = …; static struct pipe3_dpll_map dpll_map_sata[] = …; struct pipe3_data { … }; static struct pipe3_data data_usb = …; static struct pipe3_data data_sata = …; static struct pipe3_data data_pcie = …; static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) { … } static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset, u32 data) { … } static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) { … } static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy); static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy); static int ti_pipe3_power_off(struct phy *x) { … } static void ti_pipe3_calibrate(struct ti_pipe3 *phy); static int ti_pipe3_power_on(struct phy *x) { … } static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) { … } static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) { … } static void ti_pipe3_calibrate(struct ti_pipe3 *phy) { … } static int ti_pipe3_init(struct phy *x) { … } static int ti_pipe3_exit(struct phy *x) { … } static const struct phy_ops ops = …; static const struct of_device_id ti_pipe3_id_table[]; static int ti_pipe3_get_clk(struct ti_pipe3 *phy) { … } static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) { … } static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) { … } static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) { … } static int ti_pipe3_probe(struct platform_device *pdev) { … } static void ti_pipe3_remove(struct platform_device *pdev) { … } static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) { … } static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) { … } static const struct of_device_id ti_pipe3_id_table[] = …; MODULE_DEVICE_TABLE(of, ti_pipe3_id_table); static struct platform_driver ti_pipe3_driver = …; module_platform_driver(…) …; MODULE_ALIAS(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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