linux/drivers/gpu/drm/i915/display/intel_dmc_regs.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2022 Intel Corporation
 */

#ifndef __INTEL_DMC_REGS_H__
#define __INTEL_DMC_REGS_H__

#include "i915_reg_defs.h"

#define DMC_PROGRAM(addr, i) …
#define DMC_SSP_BASE_ADDR_GEN9 …

#define _PIPEDMC_CONTROL_A …
#define _PIPEDMC_CONTROL_B …
#define PIPEDMC_CONTROL(pipe) …
#define PIPEDMC_ENABLE …

#define MTL_PIPEDMC_CONTROL …
#define PIPEDMC_ENABLE_MTL(pipe) …

#define _ADLP_PIPEDMC_REG_MMIO_BASE_A …
#define _TGL_PIPEDMC_REG_MMIO_BASE_A …

#define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) …

#define __DMC_REG_MMIO_BASE …

#define _DMC_REG_MMIO_BASE(i915, dmc_id) …

#define _DMC_REG(i915, dmc_id, reg) …

#define DMC_EVENT_HANDLER_COUNT_GEN12 …

#define _DMC_EVT_HTP_0 …

#define DMC_EVT_HTP(i915, dmc_id, handler) …

#define _DMC_EVT_CTL_0 …

#define DMC_EVT_CTL(i915, dmc_id, handler) …

#define DMC_EVT_CTL_ENABLE …
#define DMC_EVT_CTL_RECURRING …
#define DMC_EVT_CTL_TYPE_MASK …
#define DMC_EVT_CTL_TYPE_LEVEL_0 …
#define DMC_EVT_CTL_TYPE_LEVEL_1 …
#define DMC_EVT_CTL_TYPE_EDGE_1_0 …
#define DMC_EVT_CTL_TYPE_EDGE_0_1 …

#define DMC_EVT_CTL_EVENT_ID_MASK …
#define DMC_EVT_CTL_EVENT_ID_FALSE …
#define DMC_EVT_CTL_EVENT_ID_VBLANK_A …
/* An event handler scheduled to run at a 1 kHz frequency. */
#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC …

#define DMC_HTP_ADDR_SKL …
#define DMC_SSP_BASE …
#define DMC_HTP_SKL …
#define DMC_LAST_WRITE …
#define DMC_LAST_WRITE_VALUE …
#define DMC_MMIO_START_RANGE …
#define DMC_MMIO_END_RANGE …
#define DMC_V1_MMIO_START_RANGE …
#define TGL_MAIN_MMIO_START …
#define TGL_MAIN_MMIO_END …
#define _TGL_PIPEA_MMIO_START …
#define _TGL_PIPEA_MMIO_END …
#define _TGL_PIPEB_MMIO_START …
#define _TGL_PIPEB_MMIO_END …
#define ADLP_PIPE_MMIO_START …
#define ADLP_PIPE_MMIO_END …

#define TGL_PIPE_MMIO_START(dmc_id) …

#define TGL_PIPE_MMIO_END(dmc_id) …

#define SKL_DMC_DC3_DC5_COUNT …
#define SKL_DMC_DC5_DC6_COUNT …
#define BXT_DMC_DC3_DC5_COUNT …
#define TGL_DMC_DEBUG_DC5_COUNT …
#define TGL_DMC_DEBUG_DC6_COUNT …
#define DG1_DMC_DEBUG_DC5_COUNT …

#define TGL_DMC_DEBUG3 …
#define DG1_DMC_DEBUG3 …

#define DMC_WAKELOCK_CFG …
#define DMC_WAKELOCK_CFG_ENABLE …
#define DMC_WAKELOCK1_CTL …
#define DMC_WAKELOCK_CTL_REQ …
#define DMC_WAKELOCK_CTL_ACK …

#endif /* __INTEL_DMC_REGS_H__ */