// SPDX-License-Identifier: MIT /* * Copyright © 2022 Intel Corporation */ #include "i915_drv.h" #include "i915_reg.h" #include "vlv_sideband_reg.h" #include "intel_display_power_map.h" #include "intel_display_power_well.h" #include "intel_display_types.h" #define __LIST_INLINE_ELEMS(__elem_type, ...) … #define __LIST(__elems) … #define I915_PW_DOMAINS(...) … #define I915_DECL_PW_DOMAINS(__name, ...) … /* Zero-length list assigns all power domains, a NULL list assigns none. */ #define I915_PW_DOMAINS_NONE … #define I915_PW_DOMAINS_ALL … #define I915_PW_INSTANCES(...) … #define I915_PW(_name, _domain_list, ...) … struct i915_power_well_desc_list { … }; #define I915_PW_DESCRIPTORS(x) … I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL); static const struct i915_power_well_desc i9xx_power_wells_always_on[] = …; static const struct i915_power_well_desc_list i9xx_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc i830_power_wells_main[] = …; static const struct i915_power_well_desc_list i830_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc hsw_power_wells_main[] = …; static const struct i915_power_well_desc_list hsw_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc bdw_power_wells_main[] = …; static const struct i915_power_well_desc_list bdw_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc vlv_power_wells_main[] = …; static const struct i915_power_well_desc_list vlv_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc chv_power_wells_main[] = …; static const struct i915_power_well_desc_list chv_power_wells[] = …; #define SKL_PW_2_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc skl_power_wells_pw_1[] = …; static const struct i915_power_well_desc skl_power_wells_main[] = …; static const struct i915_power_well_desc_list skl_power_wells[] = …; #define BXT_PW_2_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc bxt_power_wells_main[] = …; static const struct i915_power_well_desc_list bxt_power_wells[] = …; #define GLK_PW_2_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A); I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B); I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C); I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc glk_power_wells_main[] = …; static const struct i915_power_well_desc_list glk_power_wells[] = …; /* * ICL PW_0/PG_0 domains (HW/DMC control): * - PCI * - clocks except port PLL * - central power except FBC * - shared functions except pipe interrupts, pipe MBUS, DBUF registers * ICL PW_1/PG_1 domains (HW/DMC control): * - DBUF function * - PIPE_A and its planes, except VGA * - transcoder EDP + PSR * - transcoder DSI * - DDI_A * - FBC */ #define ICL_PW_4_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; /* VDSC/joining */ #define ICL_PW_3_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; /* * - transcoder WD * - KVMR (HW control) */ #define ICL_PW_2_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; /* * - KVMR (HW control) */ I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D); I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E); I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F); I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); static const struct i915_power_well_desc icl_power_wells_pw_1[] = …; static const struct i915_power_well_desc icl_power_wells_main[] = …; static const struct i915_power_well_desc_list icl_power_wells[] = …; #define TGL_PW_5_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; #define TGL_PW_4_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; #define TGL_PW_3_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1); I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2); I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3); I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4); I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5); I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5); I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6); I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc tgl_power_wells_main[] = …; static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = …; static const struct i915_power_well_desc tgl_power_wells_aux[] = …; static const struct i915_power_well_desc_list tgl_power_wells[] = …; static const struct i915_power_well_desc_list adls_power_wells[] = …; #define RKL_PW_4_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; #define RKL_PW_3_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; /* * There is no PW_2/PG_2 on RKL. * * RKL PW_1/PG_1 domains (under HW/DMC control): * - DBUF function (note: registers are in PW0) * - PIPE_A and its planes and VDSC/joining, except VGA * - transcoder A * - DDI_A and DDI_B * - FBC * * RKL PW_0/PG_0 domains (under HW/DMC control): * - PCI * - clocks except port PLL * - shared functions: * * interrupts except pipe interrupts * * MBus except PIPE_MBUS_DBOX_CTL * * DBUF registers * - central power except FBC * - top-level GTC (DDI-level GTC is in the well associated with the DDI) */ I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc rkl_power_wells_main[] = …; static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = …; static const struct i915_power_well_desc_list rkl_power_wells[] = …; /* * DG1 onwards Audio MMIO/VERBS lies in PG0 power well. */ #define DG1_PW_3_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc dg1_power_wells_main[] = …; static const struct i915_power_well_desc_list dg1_power_wells[] = …; /* * XE_LPD Power Domains * * Previous platforms required that PG(n-1) be enabled before PG(n). That * dependency chain turns into a dependency tree on XE_LPD: * * PG0 * | * --PG1-- * / \ * PGA --PG2-- * / | \ * PGB PGC PGD * * Power wells must be enabled from top to bottom and disabled from bottom * to top. This allows pipes to be power gated independently. */ #define XELPD_PW_D_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; #define XELPD_PW_C_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; #define XELPD_PW_B_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; #define XELPD_DC_OFF_PORT_POWER_DOMAINS … #define XELPD_PW_2_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; /* * XELPD PW_1/PG_1 domains (under HW/DMC control): * - DBUF function (registers are in PW0) * - Transcoder A * - DDI_A and DDI_B * * XELPD PW_0/PW_1 domains (under HW/DMC control): * - PCI * - Clocks except port PLL * - Shared functions: * * interrupts except pipe interrupts * * MBus except PIPE_MBUS_DBOX_CTL * * DBUF registers * - Central power except FBC * - Top-level GTC (DDI-level GTC is in the well associated with the DDI) */ I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc xelpd_power_wells_dc_off[] = …; static const struct i915_power_well_desc xelpd_power_wells_main[] = …; static const struct i915_power_well_desc_list xelpd_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc xehpd_power_wells_dc_off[] = …; static const struct i915_power_well_desc_list xehpd_power_wells[] = …; /* * MTL is based on XELPD power domains with the exception of power gating for: * - DDI_IO (moved to PLL logic) * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) */ #define XELPDP_PW_2_POWER_DOMAINS … I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc xelpdp_power_wells_main[] = …; static const struct i915_power_well_desc_list xelpdp_power_wells[] = …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = …; I915_DECL_PW_DOMAINS(…) …; static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = …; static const struct i915_power_well_desc_list xe2lpd_power_wells[] = …; static void init_power_well_domains(const struct i915_power_well_instance *inst, struct i915_power_well *power_well) { … } #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) … #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) … static int __set_power_wells(struct i915_power_domains *power_domains, const struct i915_power_well_desc_list *power_well_descs, int power_well_descs_sz) { … } #define set_power_wells(power_domains, __power_well_descs) … /** * intel_display_power_map_init - initialize power domain -> power well mappings * @power_domains: power domain state * * Creates all the power wells for the current platform, initializes the * dynamic state for them and initializes the mapping of each power well to * all the power domains the power well belongs to. */ int intel_display_power_map_init(struct i915_power_domains *power_domains) { … } /** * intel_display_power_map_cleanup - clean up power domain -> power well mappings * @power_domains: power domain state * * Cleans up all the state that was initialized by intel_display_power_map_init(). */ void intel_display_power_map_cleanup(struct i915_power_domains *power_domains) { … }
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