// SPDX-License-Identifier: GPL-2.0 /* * Wrapper driver for SERDES used in J721E * * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ * Author: Kishon Vijay Abraham I <[email protected]> */ #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-ti.h> #include <linux/slab.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/gpio.h> #include <linux/gpio/consumer.h> #include <linux/io.h> #include <linux/module.h> #include <linux/mfd/syscon.h> #include <linux/mux/consumer.h> #include <linux/of_address.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset-controller.h> #define REF_CLK_19_2MHZ … #define REF_CLK_25MHZ … #define REF_CLK_100MHZ … #define REF_CLK_156_25MHZ … /* SCM offsets */ #define SERDES_SUP_CTRL … /* SERDES offsets */ #define WIZ_SERDES_CTRL … #define WIZ_SERDES_TOP_CTRL … #define WIZ_SERDES_RST … #define WIZ_SERDES_TYPEC … #define WIZ_LANECTL(n) … #define WIZ_LANEDIV(n) … #define WIZ_MAX_INPUT_CLOCKS … /* To include mux clocks, divider clocks and gate clocks */ #define WIZ_MAX_OUTPUT_CLOCKS … #define WIZ_MAX_LANES … #define WIZ_MUX_NUM_CLOCKS … #define WIZ_DIV_NUM_CLOCKS_16G … #define WIZ_DIV_NUM_CLOCKS_10G … #define WIZ_SERDES_TYPEC_LN10_SWAP … enum wiz_lane_standard_mode { … }; /* * List of master lanes used for lane swapping */ enum wiz_typec_master_lane { … }; enum wiz_refclk_mux_sel { … }; enum wiz_refclk_div_sel { … }; enum wiz_clock_input { … }; static const struct reg_field por_en = …; static const struct reg_field phy_reset_n = …; static const struct reg_field phy_en_refclk = …; static const struct reg_field pll1_refclk_mux_sel = …; static const struct reg_field pll1_refclk_mux_sel_2 = …; static const struct reg_field pll0_refclk_mux_sel = …; static const struct reg_field pll0_refclk_mux_sel_2 = …; static const struct reg_field refclk_dig_sel_16g = …; static const struct reg_field refclk_dig_sel_10g = …; static const struct reg_field pma_cmn_refclk_int_mode = …; static const struct reg_field pma_cmn_refclk1_int_mode = …; static const struct reg_field pma_cmn_refclk_mode = …; static const struct reg_field pma_cmn_refclk_dig_div = …; static const struct reg_field pma_cmn_refclk1_dig_div = …; static const struct reg_field sup_pll0_refclk_mux_sel = …; static const struct reg_field sup_pll1_refclk_mux_sel = …; static const struct reg_field sup_pma_cmn_refclk1_int_mode = …; static const struct reg_field sup_refclk_dig_sel_10g = …; static const struct reg_field sup_legacy_clk_override = …; static const char * const output_clk_names[] = …; static const struct reg_field p_enable[WIZ_MAX_LANES] = …; enum p_enable { … }; static const struct reg_field p_align[WIZ_MAX_LANES] = …; static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = …; static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = …; static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = …; static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = …; static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = …; static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = …; static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = …; static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = …; static const struct reg_field typec_ln10_swap = …; static const struct reg_field typec_ln23_swap = …; struct wiz_clk_mux { … }; #define to_wiz_clk_mux(_hw) … struct wiz_clk_divider { … }; #define to_wiz_clk_div(_hw) … struct wiz_clk_mux_sel { … }; struct wiz_clk_div_sel { … }; struct wiz_phy_en_refclk { … }; #define to_wiz_phy_en_refclk(_hw) … static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = …; static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = …; static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = …; static const struct clk_div_table clk_div_table[] = …; static const struct wiz_clk_div_sel clk_div_sel[] = …; enum wiz_type { … }; struct wiz_data { … }; #define WIZ_TYPEC_DIR_DEBOUNCE_MIN … #define WIZ_TYPEC_DIR_DEBOUNCE_MAX … struct wiz { … }; static int wiz_reset(struct wiz *wiz) { … } static int wiz_p_mac_div_sel(struct wiz *wiz) { … } static int wiz_mode_select(struct wiz *wiz) { … } static int wiz_init_raw_interface(struct wiz *wiz, bool enable) { … } static int wiz_init(struct wiz *wiz) { … } static int wiz_regfield_init(struct wiz *wiz) { … } static int wiz_phy_en_refclk_enable(struct clk_hw *hw) { … } static void wiz_phy_en_refclk_disable(struct clk_hw *hw) { … } static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops wiz_phy_en_refclk_ops = …; static int wiz_phy_en_refclk_register(struct wiz *wiz) { … } static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) { … } static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops wiz_clk_mux_ops = …; static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, const struct wiz_clk_mux_sel *mux_sel, int clk_index) { … } static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, struct regmap_field *field, const u32 *table) { … } static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops wiz_clk_div_ops = …; static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, struct regmap_field *field, const struct clk_div_table *table) { … } static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) { … } static int wiz_clock_register(struct wiz *wiz) { … } static void wiz_clock_init(struct wiz *wiz) { … } static int wiz_clock_probe(struct wiz *wiz, struct device_node *node) { … } static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { … } static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) { … } static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { … } static const struct reset_control_ops wiz_phy_reset_ops = …; static const struct regmap_config wiz_regmap_config = …; static struct wiz_data j721e_16g_data = …; static struct wiz_data j721e_10g_data = …; static struct wiz_data am64_10g_data = …; static struct wiz_data j7200_pg2_10g_data = …; static struct wiz_data j784s4_10g_data = …; static struct wiz_data j721s2_10g_data = …; static const struct of_device_id wiz_id_table[] = …; MODULE_DEVICE_TABLE(of, wiz_id_table); static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) { … } static int wiz_probe(struct platform_device *pdev) { … } static void wiz_remove(struct platform_device *pdev) { … } static int wiz_resume_noirq(struct device *dev) { … } static DEFINE_NOIRQ_DEV_PM_OPS(wiz_pm_ops, NULL, wiz_resume_noirq); static struct platform_driver wiz_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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