/* * Copyright © 2006-2007 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Eric Anholt <[email protected]> */ #include <linux/dma-resv.h> #include <linux/i2c.h> #include <linux/input.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/string_helpers.h> #include <drm/display/drm_dp_helper.h> #include <drm/display/drm_dp_tunnel.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_atomic_uapi.h> #include <drm/drm_damage_helper.h> #include <drm/drm_edid.h> #include <drm/drm_fixed.h> #include <drm/drm_fourcc.h> #include <drm/drm_probe_helper.h> #include <drm/drm_rect.h> #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_object.h" #include "g4x_dp.h" #include "g4x_hdmi.h" #include "hsw_ips.h" #include "i915_config.h" #include "i915_drv.h" #include "i915_reg.h" #include "i915_utils.h" #include "i9xx_plane.h" #include "i9xx_plane_regs.h" #include "i9xx_wm.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_audio.h" #include "intel_bw.h" #include "intel_cdclk.h" #include "intel_clock_gating.h" #include "intel_color.h" #include "intel_crt.h" #include "intel_crtc.h" #include "intel_crtc_state_dump.h" #include "intel_cursor_regs.h" #include "intel_cx0_phy.h" #include "intel_cursor.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" #include "intel_display_power.h" #include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" #include "intel_dp_tunnel.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" #include "intel_dpt.h" #include "intel_dpt_common.h" #include "intel_drrs.h" #include "intel_dsb.h" #include "intel_dsi.h" #include "intel_dvo.h" #include "intel_fb.h" #include "intel_fbc.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h" #include "intel_hotplug.h" #include "intel_link_bw.h" #include "intel_lvds.h" #include "intel_lvds_regs.h" #include "intel_modeset_setup.h" #include "intel_modeset_verify.h" #include "intel_overlay.h" #include "intel_panel.h" #include "intel_pch_display.h" #include "intel_pch_refclk.h" #include "intel_pcode.h" #include "intel_pipe_crc.h" #include "intel_plane_initial.h" #include "intel_pmdemand.h" #include "intel_pps.h" #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_sdvo.h" #include "intel_snps_phy.h" #include "intel_tc.h" #include "intel_tdf.h" #include "intel_tv.h" #include "intel_vblank.h" #include "intel_vdsc.h" #include "intel_vdsc_regs.h" #include "intel_vga.h" #include "intel_vrr.h" #include "intel_wm.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_universal_plane_regs.h" #include "skl_watermark.h" #include "vlv_dpio_phy_regs.h" #include "vlv_dsi.h" #include "vlv_dsi_pll.h" #include "vlv_dsi_regs.h" #include "vlv_sideband.h" static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state); /* returns HPLL frequency in kHz */ int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) { … } int vlv_get_cck_clock(struct drm_i915_private *dev_priv, const char *name, u32 reg, int ref_freq) { … } int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, const char *name, u32 reg) { … } void intel_update_czclk(struct drm_i915_private *dev_priv) { … } static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) { … } /* WA Display #0827: Gen9:all */ static void skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { … } /* Wa_2006604312:icl,ehl */ static void icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { … } /* Wa_1604331009:icl,jsl,ehl */ static void icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { … } static bool is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) { … } bool is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) { … } bool is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) { … } static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) { … } u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) { … } bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) { … } bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) { … } static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) { … } u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) { … } struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) { … } static void intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) { … } void assert_transcoder(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder, bool state) { … } static void assert_plane(struct intel_plane *plane, bool state) { … } #define assert_plane_enabled(p) … #define assert_plane_disabled(p) … static void assert_planes_disabled(struct intel_crtc *crtc) { … } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, struct intel_digital_port *dig_port, unsigned int expected_mask) { … } void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) { … } void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) { … } unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) { … } unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) { … } bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) { … } /* * Convert the x/y offsets into a linear offset. * Only valid with 0/180 degree rotation, which is fine since linear * offset is only used with linear buffers on pre-hsw and tiled buffers * with gen2/3, and 90/270 degree rotations isn't supported on any of them. */ u32 intel_fb_xy_to_linear(int x, int y, const struct intel_plane_state *state, int color_plane) { … } /* * Add the x/y offsets derived from fb->offsets[] to the user * specified plane src x/y offsets. The resulting x/y offsets * specify the start of scanout from the beginning of the gtt mapping. */ void intel_add_fb_offsets(int *x, int *y, const struct intel_plane_state *state, int color_plane) { … } u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier) { … } void intel_set_plane_visible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state, bool visible) { … } void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) { … } void intel_plane_disable_noatomic(struct intel_crtc *crtc, struct intel_plane *plane) { … } unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) { … } static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) { … } bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) { … } /* * Finds the encoder associated with the given CRTC. This can only be * used when we know that the CRTC isn't feeding multiple encoders! */ struct intel_encoder * intel_get_crtc_new_encoder(const struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state) { … } static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) { … } static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) { … } static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) { … } static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) { … } static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) { … } static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, enum pipe pipe, bool enable) { … } static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) { … } static void intel_encoders_audio_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_audio_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } #define is_enabling … #define is_disabling … static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } #undef is_disabling #undef is_enabling static void intel_post_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_crtc_disable_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_update_prepare(struct intel_atomic_state *state) { … } static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_pre_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_post_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_encoders_update_pipe(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) { … } static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) { … } static void ilk_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } /* Display WA #1180: WaDisableScalarClockGating: glk */ static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) { … } static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) { … } static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) { … } static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) { … } static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) { … } static void hsw_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) { … } static void ilk_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void hsw_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) { … } /* Prefer intel_encoder_is_combo() */ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { … } /* Prefer intel_encoder_is_tc() */ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { … } /* Prefer intel_encoder_is_snps() */ bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) { … } /* Prefer intel_encoder_to_phy() */ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { … } /* Prefer intel_encoder_to_tc() */ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) { … } enum phy intel_encoder_to_phy(struct intel_encoder *encoder) { … } bool intel_encoder_is_combo(struct intel_encoder *encoder) { … } bool intel_encoder_is_snps(struct intel_encoder *encoder) { … } bool intel_encoder_is_tc(struct intel_encoder *encoder) { … } enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) { … } enum intel_display_power_domain intel_aux_power_domain(struct intel_digital_port *dig_port) { … } static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *mask) { … } void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *old_domains) { … } void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, struct intel_power_domain_mask *domains) { … } static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) { … } static void valleyview_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void i9xx_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) { … } static void i9xx_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } void intel_encoder_destroy(struct drm_encoder *encoder) { … } static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) { … } static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) { … } static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, const struct drm_display_mode *timings) { … } static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) { … } static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, struct drm_display_mode *mode) { … } static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, struct drm_display_mode *mode) { … } static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) { … } void intel_encoder_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { … } static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) { … } static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) { … } static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) { … } static int intel_crtc_compute_config(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_reduce_m_n_ratio(u32 *num, u32 *den) { … } static void compute_m_n(u32 *ret_m, u32 *ret_n, u32 m, u32 n, u32 constant_n) { … } void intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, int pixel_clock, int link_clock, int bw_overhead, struct intel_link_m_n *m_n) { … } void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) { … } void intel_zero_m_n(struct intel_link_m_n *m_n) { … } void intel_set_m_n(struct drm_i915_private *i915, const struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { … } bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, enum transcoder transcoder) { … } void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, enum transcoder transcoder, const struct intel_link_m_n *m_n) { … } void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, enum transcoder transcoder, const struct intel_link_m_n *m_n) { … } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) { … } static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) { … } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) { … } static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) { … } static void intel_get_transcoder_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { … } static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) { … } static void intel_get_pipe_src_size(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { … } void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) { … } static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) { … } static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) { … } static enum intel_output_format bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) { … } static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { … } void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) { … } static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) { … } static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) { … } int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) { … } int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) { … } void intel_get_m_n(struct drm_i915_private *i915, struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { … } void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, enum transcoder transcoder, struct intel_link_m_n *m_n) { … } void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, enum transcoder transcoder, struct intel_link_m_n *m_n) { … } static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) { … } static bool ilk_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { … } static u8 joiner_pipes(struct drm_i915_private *i915) { … } static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { … } static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, u8 *primary_pipes, u8 *secondary_pipes) { … } static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) { … } static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) { … } static u8 hsw_panel_transcoders(struct drm_i915_private *i915) { … } static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) { … } static bool has_edp_transcoders(u8 enabled_transcoders) { … } static bool has_dsi_transcoders(u8 enabled_transcoders) { … } static bool has_pipe_transcoders(u8 enabled_transcoders) { … } static void assert_enabled_transcoders(struct drm_i915_private *i915, u8 enabled_transcoders) { … } static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) { … } static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) { … } static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) { … } static bool hsw_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { … } bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) { … } int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n) { … } int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) { … } /* Returns the currently programmed mode of the given encoder. */ struct drm_display_mode * intel_encoder_current_mode(struct intel_encoder *encoder) { … } static bool encoders_cloneable(const struct intel_encoder *a, const struct intel_encoder *b) { … } static bool check_single_encoder_cloning(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int icl_add_linked_planes(struct intel_atomic_state *state) { … } static int icl_check_nv12_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { … } static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, const struct intel_cdclk_state *cdclk_state) { … } static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) { … } static int hsw_compute_linetime_wm(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int intel_crtc_atomic_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, struct intel_crtc_state *crtc_state) { … } static int compute_baseline_pipe_bpp(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool check_digital_port_conflicts(struct intel_atomic_state *state) { … } static void intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, struct intel_crtc *secondary_crtc) { … } static int copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, struct intel_crtc *secondary_crtc) { … } static int intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int intel_modeset_pipe_config(struct intel_atomic_state *state, struct intel_crtc *crtc, const struct intel_link_bw_limits *limits) { … } static int intel_modeset_pipe_config_late(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } bool intel_fuzzy_clock_check(int clock1, int clock2) { … } static bool intel_compare_link_m_n(const struct intel_link_m_n *m_n, const struct intel_link_m_n *m2_n2) { … } static bool intel_compare_infoframe(const union hdmi_infoframe *a, const union hdmi_infoframe *b) { … } static bool intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, const struct drm_dp_vsc_sdp *b) { … } static bool intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, const struct drm_dp_as_sdp *b) { … } static bool intel_compare_buffer(const u8 *a, const u8 *b, size_t len) { … } static void __printf(5, 6) pipe_config_mismatch(struct drm_printer *p, bool fastset, const struct intel_crtc *crtc, const char *name, const char *format, ...) { … } static void pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, const struct intel_crtc *crtc, const char *name, const union hdmi_infoframe *a, const union hdmi_infoframe *b) { … } static void pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset, const struct intel_crtc *crtc, const char *name, const struct drm_dp_vsc_sdp *a, const struct drm_dp_vsc_sdp *b) { … } static void pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915, bool fastset, const char *name, const struct drm_dp_as_sdp *a, const struct drm_dp_as_sdp *b) { … } /* Returns the length up to and including the last differing byte */ static size_t memcmp_diff_len(const u8 *a, const u8 *b, size_t len) { … } static void pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset, const struct intel_crtc *crtc, const char *name, const u8 *a, const u8 *b, size_t len) { … } static void pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, const struct intel_crtc *crtc, const char *name, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b) { … } static void pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, const struct intel_crtc *crtc, const char *name, const struct intel_cx0pll_state *a, const struct intel_cx0pll_state *b) { … } bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, bool fastset) { … } static void intel_verify_planes(struct intel_atomic_state *state) { … } static int intel_modeset_pipe(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state, const char *reason) { … } /** * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes * @state: intel atomic state * @reason: the reason for the full modeset * @mask: mask of pipes to modeset * * Add pipes in @mask to @state and force a full modeset on the enabled ones * due to the description in @reason. * This function can be called only before new plane states are computed. * * Returns 0 in case of success, negative error code otherwise. */ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 mask) { … } static void intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) { … } /** * intel_modeset_all_pipes_late - force a full modeset on all pipes * @state: intel atomic state * @reason: the reason for the full modeset * * Add all pipes to @state and force a full modeset on the active ones due to * the description in @reason. * This function can be called only after new plane states are computed already. * * Returns 0 in case of success, negative error code otherwise. */ int intel_modeset_all_pipes_late(struct intel_atomic_state *state, const char *reason) { … } int intel_modeset_commit_pipes(struct drm_i915_private *i915, u8 pipe_mask, struct drm_modeset_acquire_ctx *ctx) { … } /* * This implements the workaround described in the "notes" section of the mode * set sequence documentation. When going from no pipes or single pipe to * multiple pipes, and planes are enabled after the pipe, we need to wait at * least 2 vblanks on the first pipe before enabling planes on the second pipe. */ static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) { … } u8 intel_calc_active_pipes(struct intel_atomic_state *state, u8 active_pipes) { … } static int intel_modeset_checks(struct intel_atomic_state *state) { … } static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, struct intel_crtc_state *new_crtc_state) { … } static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, struct intel_crtc *crtc, u8 plane_ids_mask) { … } int intel_atomic_add_affected_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) { … } static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_crtc *other) { … } static int intel_joiner_add_affected_planes(struct intel_atomic_state *state) { … } static int intel_atomic_check_planes(struct intel_atomic_state *state) { … } static int intel_atomic_check_crtcs(struct intel_atomic_state *state) { … } static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, u8 transcoders) { … } static bool intel_pipes_need_modeset(struct intel_atomic_state *state, u8 pipes) { … } static int intel_atomic_check_joiner(struct intel_atomic_state *state, struct intel_crtc *primary_crtc) { … } static void kill_joiner_secondaries(struct intel_atomic_state *state, struct intel_crtc *primary_crtc) { … } /** * DOC: asynchronous flip implementation * * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. * Correspondingly, support is currently added for primary plane only. * * Async flip can only change the plane surface address, so anything else * changing is rejected from the intel_async_flip_check_hw() function. * Once this check is cleared, flip done interrupt is enabled using * the intel_crtc_enable_flip_done() function. * * As soon as the surface address register is written, flip done interrupt is * generated and the requested events are sent to the usersapce in the interrupt * handler itself. The timestamp and sequence sent during the flip done event * correspond to the last vblank and have no relation to the actual time when * the flip done event was sent. */ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) { … } static int intel_atomic_check_config(struct intel_atomic_state *state, struct intel_link_bw_limits *limits, enum pipe *failed_pipe) { … } static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) { … } /** * intel_atomic_check - validate state object * @dev: drm device * @_state: state to validate */ int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *_state) { … } static int intel_atomic_prepare_commit(struct intel_atomic_state *state) { … } void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state) { … } static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { … } static void commit_pipe_pre_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void commit_pipe_post_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_enable_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_pre_update_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_update_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_old_crtc_state_disables(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static void intel_commit_modeset_disables(struct intel_atomic_state *state) { … } static void intel_commit_modeset_enables(struct intel_atomic_state *state) { … } static void skl_commit_modeset_enables(struct intel_atomic_state *state) { … } static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) { … } static void intel_atomic_cleanup_work(struct work_struct *work) { … } static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) { … } static void intel_atomic_commit_tail(struct intel_atomic_state *state) { … } static void intel_atomic_commit_work(struct work_struct *work) { … } static void intel_atomic_track_fbs(struct intel_atomic_state *state) { … } static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock) { … } static int intel_atomic_swap_state(struct intel_atomic_state *state) { … } int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, bool nonblock) { … } /** * intel_plane_destroy - destroy a plane * @plane: plane to destroy * * Common destruction function for all types of planes (primary, cursor, * sprite). */ void intel_plane_destroy(struct drm_plane *plane) { … } int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { … } static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) { … } static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) { … } static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) { … } static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) { … } bool assert_port_valid(struct drm_i915_private *i915, enum port port) { … } void intel_setup_outputs(struct drm_i915_private *dev_priv) { … } static int max_dotclock(struct drm_i915_private *i915) { … } enum drm_mode_status intel_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode) { … } enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, const struct drm_display_mode *mode) { … } enum drm_mode_status intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, const struct drm_display_mode *mode, bool joiner) { … } static const struct intel_display_funcs skl_display_funcs = …; static const struct intel_display_funcs ddi_display_funcs = …; static const struct intel_display_funcs pch_split_display_funcs = …; static const struct intel_display_funcs vlv_display_funcs = …; static const struct intel_display_funcs i9xx_display_funcs = …; /** * intel_init_display_hooks - initialize the display modesetting hooks * @dev_priv: device private */ void intel_init_display_hooks(struct drm_i915_private *dev_priv) { … } int intel_initial_commit(struct drm_device *dev) { … } void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { … } void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { … } void intel_hpd_poll_fini(struct drm_i915_private *i915) { … } bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) { … }
Codebase Browser
linux