/* SPDX-License-Identifier: GPL-2.0 */ /* * Lochnagar1 register definitions * * Copyright (c) 2017-2018 Cirrus Logic, Inc. and * Cirrus Logic International Semiconductor Ltd. * * Author: Charles Keepax <[email protected]> */ #ifndef LOCHNAGAR1_REGISTERS_H #define LOCHNAGAR1_REGISTERS_H /* Register Addresses */ #define LOCHNAGAR1_CDC_AIF1_SEL … #define LOCHNAGAR1_CDC_AIF2_SEL … #define LOCHNAGAR1_CDC_AIF3_SEL … #define LOCHNAGAR1_CDC_MCLK1_SEL … #define LOCHNAGAR1_CDC_MCLK2_SEL … #define LOCHNAGAR1_CDC_AIF_CTRL1 … #define LOCHNAGAR1_CDC_AIF_CTRL2 … #define LOCHNAGAR1_EXT_AIF_CTRL … #define LOCHNAGAR1_DSP_AIF1_SEL … #define LOCHNAGAR1_DSP_AIF2_SEL … #define LOCHNAGAR1_DSP_CLKIN_SEL … #define LOCHNAGAR1_DSP_AIF … #define LOCHNAGAR1_GF_AIF1 … #define LOCHNAGAR1_GF_AIF2 … #define LOCHNAGAR1_PSIA_AIF … #define LOCHNAGAR1_PSIA1_SEL … #define LOCHNAGAR1_PSIA2_SEL … #define LOCHNAGAR1_SPDIF_AIF_SEL … #define LOCHNAGAR1_GF_AIF3_SEL … #define LOCHNAGAR1_GF_AIF4_SEL … #define LOCHNAGAR1_GF_CLKOUT1_SEL … #define LOCHNAGAR1_GF_AIF1_SEL … #define LOCHNAGAR1_GF_AIF2_SEL … #define LOCHNAGAR1_GF_GPIO2 … #define LOCHNAGAR1_GF_GPIO3 … #define LOCHNAGAR1_GF_GPIO7 … #define LOCHNAGAR1_RST … #define LOCHNAGAR1_LED1 … #define LOCHNAGAR1_LED2 … #define LOCHNAGAR1_I2C_CTRL … /* * (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020) * CDC_AIF1_SEL - GF_AIF2_SEL */ #define LOCHNAGAR1_SRC_MASK … #define LOCHNAGAR1_SRC_SHIFT … /* (0x000D) CDC_AIF_CTRL1 */ #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK … #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK … #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT … #define LOCHNAGAR1_CDC_AIF2_ENA_MASK … #define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT … #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK … #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK … #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT … #define LOCHNAGAR1_CDC_AIF1_ENA_MASK … #define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT … /* (0x000E) CDC_AIF_CTRL2 */ #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK … #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK … #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT … #define LOCHNAGAR1_CDC_AIF3_ENA_MASK … #define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT … #define LOCHNAGAR1_CDC_MCLK1_ENA_MASK … #define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT … #define LOCHNAGAR1_CDC_MCLK2_ENA_MASK … #define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT … /* (0x000F) EXT_AIF_CTRL */ #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK … #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK … #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT … #define LOCHNAGAR1_SPDIF_AIF_ENA_MASK … #define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT … /* (0x0013) DSP_AIF */ #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK … #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK … #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT … #define LOCHNAGAR1_DSP_AIF2_ENA_MASK … #define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT … #define LOCHNAGAR1_DSP_CLKIN_ENA_MASK … #define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT … #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK … #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK … #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT … #define LOCHNAGAR1_DSP_AIF1_ENA_MASK … #define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT … /* (0x0014) GF_AIF1 */ #define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK … #define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT … #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF3_ENA_MASK … #define LOCHNAGAR1_GF_AIF3_ENA_SHIFT … #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF1_ENA_MASK … #define LOCHNAGAR1_GF_AIF1_ENA_SHIFT … /* (0x0015) GF_AIF2 */ #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF4_ENA_MASK … #define LOCHNAGAR1_GF_AIF4_ENA_SHIFT … #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK … #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT … #define LOCHNAGAR1_GF_AIF2_ENA_MASK … #define LOCHNAGAR1_GF_AIF2_ENA_SHIFT … /* (0x0016) PSIA_AIF */ #define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK … #define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK … #define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT … #define LOCHNAGAR1_PSIA2_ENA_MASK … #define LOCHNAGAR1_PSIA2_ENA_SHIFT … #define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK … #define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT … #define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK … #define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT … #define LOCHNAGAR1_PSIA1_ENA_MASK … #define LOCHNAGAR1_PSIA1_ENA_SHIFT … /* (0x0029) RST */ #define LOCHNAGAR1_DSP_RESET_MASK … #define LOCHNAGAR1_DSP_RESET_SHIFT … #define LOCHNAGAR1_CDC_RESET_MASK … #define LOCHNAGAR1_CDC_RESET_SHIFT … /* (0x0046) I2C_CTRL */ #define LOCHNAGAR1_CDC_CIF_MODE_MASK … #define LOCHNAGAR1_CDC_CIF_MODE_SHIFT … #endif
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