// SPDX-License-Identifier: GPL-2.0 /* * Cherryview/Braswell pinctrl driver * * Copyright (C) 2014, 2020 Intel Corporation * Author: Mika Westerberg <[email protected]> * * This driver is based on the original Cherryview GPIO driver by * Ning Li <[email protected]> * Alan Cox <[email protected]> */ #include <linux/acpi.h> #include <linux/array_size.h> #include <linux/cleanup.h> #include <linux/dmi.h> #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/seq_file.h> #include <linux/types.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include "pinctrl-intel.h" #define CHV_INTSTAT … #define CHV_INTMASK … #define FAMILY_PAD_REGS_OFF … #define FAMILY_PAD_REGS_SIZE … #define MAX_FAMILY_PAD_GPIO_NO … #define GPIO_REGS_SIZE … #define CHV_PADCTRL0 … #define CHV_PADCTRL0_INTSEL_SHIFT … #define CHV_PADCTRL0_INTSEL_MASK … #define CHV_PADCTRL0_TERM_UP … #define CHV_PADCTRL0_TERM_SHIFT … #define CHV_PADCTRL0_TERM_MASK … #define CHV_PADCTRL0_TERM_20K … #define CHV_PADCTRL0_TERM_5K … #define CHV_PADCTRL0_TERM_1K … #define CHV_PADCTRL0_PMODE_SHIFT … #define CHV_PADCTRL0_PMODE_MASK … #define CHV_PADCTRL0_GPIOEN … #define CHV_PADCTRL0_GPIOCFG_SHIFT … #define CHV_PADCTRL0_GPIOCFG_MASK … #define CHV_PADCTRL0_GPIOCFG_GPIO … #define CHV_PADCTRL0_GPIOCFG_GPO … #define CHV_PADCTRL0_GPIOCFG_GPI … #define CHV_PADCTRL0_GPIOCFG_HIZ … #define CHV_PADCTRL0_GPIOTXSTATE … #define CHV_PADCTRL0_GPIORXSTATE … #define CHV_PADCTRL1 … #define CHV_PADCTRL1_CFGLOCK … #define CHV_PADCTRL1_INVRXTX_SHIFT … #define CHV_PADCTRL1_INVRXTX_MASK … #define CHV_PADCTRL1_INVRXTX_TXDATA … #define CHV_PADCTRL1_INVRXTX_RXDATA … #define CHV_PADCTRL1_INVRXTX_TXENABLE … #define CHV_PADCTRL1_ODEN … #define CHV_PADCTRL1_INTWAKECFG_MASK … #define CHV_PADCTRL1_INTWAKECFG_FALLING … #define CHV_PADCTRL1_INTWAKECFG_RISING … #define CHV_PADCTRL1_INTWAKECFG_BOTH … #define CHV_PADCTRL1_INTWAKECFG_LEVEL … struct intel_pad_context { … }; #define CHV_INVALID_HWIRQ … /** * struct intel_community_context - community context for Cherryview * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) * @saved_intmask: Interrupt mask saved for system sleep */ struct intel_community_context { … }; #define PINMODE_INVERT_OE … #define PINMODE(m, i) … #define CHV_GPP(start, end) … #define CHV_COMMUNITY(g, i, a) … static const struct pinctrl_pin_desc southwest_pins[] = …; static const unsigned southwest_uart0_pins[] = …; static const unsigned southwest_uart1_pins[] = …; static const unsigned southwest_uart2_pins[] = …; static const unsigned southwest_i2c0_pins[] = …; static const unsigned southwest_hda_pins[] = …; static const unsigned southwest_lpe_pins[] = …; static const unsigned southwest_i2c1_pins[] = …; static const unsigned southwest_i2c2_pins[] = …; static const unsigned southwest_i2c3_pins[] = …; static const unsigned southwest_i2c4_pins[] = …; static const unsigned southwest_i2c5_pins[] = …; static const unsigned southwest_i2c6_pins[] = …; static const unsigned southwest_i2c_nfc_pins[] = …; static const unsigned southwest_spi3_pins[] = …; /* Some of LPE I2S TXD pins need to have OE inversion set */ static const unsigned int southwest_lpe_altfuncs[] = …; /* * Two spi3 chipselects are available in different mode than the main spi3 * functionality, which is using mode 2. */ static const unsigned int southwest_spi3_altfuncs[] = …; static const struct intel_pingroup southwest_groups[] = …; static const char * const southwest_uart0_groups[] = …; static const char * const southwest_uart1_groups[] = …; static const char * const southwest_uart2_groups[] = …; static const char * const southwest_hda_groups[] = …; static const char * const southwest_lpe_groups[] = …; static const char * const southwest_i2c0_groups[] = …; static const char * const southwest_i2c1_groups[] = …; static const char * const southwest_i2c2_groups[] = …; static const char * const southwest_i2c3_groups[] = …; static const char * const southwest_i2c4_groups[] = …; static const char * const southwest_i2c5_groups[] = …; static const char * const southwest_i2c6_groups[] = …; static const char * const southwest_i2c_nfc_groups[] = …; static const char * const southwest_spi3_groups[] = …; /* * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are * enabled only as GPIOs. */ static const struct intel_function southwest_functions[] = …; static const struct intel_padgroup southwest_gpps[] = …; /* * Southwest community can generate GPIO interrupts only for the first 8 * interrupts. The upper half (8-15) can only be used to trigger GPEs. */ static const struct intel_community southwest_communities[] = …; static const struct intel_pinctrl_soc_data southwest_soc_data = …; static const struct pinctrl_pin_desc north_pins[] = …; static const struct intel_padgroup north_gpps[] = …; /* * North community can generate GPIO interrupts only for the first 8 * interrupts. The upper half (8-15) can only be used to trigger GPEs. */ static const struct intel_community north_communities[] = …; static const struct intel_pinctrl_soc_data north_soc_data = …; static const struct pinctrl_pin_desc east_pins[] = …; static const struct intel_padgroup east_gpps[] = …; static const struct intel_community east_communities[] = …; static const struct intel_pinctrl_soc_data east_soc_data = …; static const struct pinctrl_pin_desc southeast_pins[] = …; static const unsigned southeast_pwm0_pins[] = …; static const unsigned southeast_pwm1_pins[] = …; static const unsigned southeast_sdmmc1_pins[] = …; static const unsigned southeast_sdmmc2_pins[] = …; static const unsigned southeast_sdmmc3_pins[] = …; static const unsigned southeast_spi1_pins[] = …; static const unsigned southeast_spi2_pins[] = …; static const struct intel_pingroup southeast_groups[] = …; static const char * const southeast_pwm0_groups[] = …; static const char * const southeast_pwm1_groups[] = …; static const char * const southeast_sdmmc1_groups[] = …; static const char * const southeast_sdmmc2_groups[] = …; static const char * const southeast_sdmmc3_groups[] = …; static const char * const southeast_spi1_groups[] = …; static const char * const southeast_spi2_groups[] = …; static const struct intel_function southeast_functions[] = …; static const struct intel_padgroup southeast_gpps[] = …; static const struct intel_community southeast_communities[] = …; static const struct intel_pinctrl_soc_data southeast_soc_data = …; static const struct intel_pinctrl_soc_data *chv_soc_data[] = …; /* * Lock to serialize register accesses * * Due to a silicon issue, a shared lock must be used to prevent * concurrent accesses across the 4 GPIO controllers. * * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), * errata #CHT34, for further information. */ static DEFINE_RAW_SPINLOCK(chv_lock); static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) { … } static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value) { … } static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset, unsigned int reg) { … } static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset) { … } static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) { … } /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ static bool chv_pad_is_locked(u32 ctrl1) { … } static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) { … } static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int offset) { … } static const struct pinctrl_ops chv_pinctrl_ops = …; static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { … } static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, unsigned int offset) { … } static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { … } static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { … } static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, bool input) { … } static const struct pinmux_ops chv_pinmux_ops = …; static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { … } static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 arg) { … } static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, bool enable) { … } static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int nconfigs) { … } static int chv_config_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { … } static int chv_config_group_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *configs, unsigned int num_configs) { … } static const struct pinconf_ops chv_pinconf_ops = …; static struct pinctrl_desc chv_pinctrl_desc = …; static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) { … } static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { … } static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { … } static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { … } static const struct gpio_chip chv_gpio_chip = …; static void chv_gpio_irq_ack(struct irq_data *d) { … } static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) { … } static void chv_gpio_irq_mask(struct irq_data *d) { … } static void chv_gpio_irq_unmask(struct irq_data *d) { … } static unsigned chv_gpio_irq_startup(struct irq_data *d) { … } static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) { … } static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) { … } static const struct irq_chip chv_gpio_irq_chip = …; static void chv_gpio_irq_handler(struct irq_desc *desc) { … } /* * Certain machines seem to hardcode Linux IRQ numbers in their ACPI * tables. Since we leave GPIOs that are not capable of generating * interrupts out of the irqdomain the numbering will be different and * cause devices using the hardcoded IRQ numbers fail. In order not to * break such machines we will only mask pins from irqdomain if the machine * is not listed below. */ static const struct dmi_system_id chv_no_valid_mask[] = …; static void chv_init_irq_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) { … } static int chv_gpio_irq_init_hw(struct gpio_chip *chip) { … } static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) { … } static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) { … } static acpi_status chv_pinctrl_mmio_access_handler(u32 function, acpi_physical_address address, u32 bits, u64 *value, void *handler_context, void *region_context) { … } static int chv_pinctrl_probe(struct platform_device *pdev) { … } static void chv_pinctrl_remove(struct platform_device *pdev) { … } static int chv_pinctrl_suspend_noirq(struct device *dev) { … } static int chv_pinctrl_resume_noirq(struct device *dev) { … } static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops, chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq); static const struct acpi_device_id chv_pinctrl_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); static struct platform_driver chv_pinctrl_driver = …; static int __init chv_pinctrl_init(void) { … } subsys_initcall(chv_pinctrl_init); static void __exit chv_pinctrl_exit(void) { … } module_exit(chv_pinctrl_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_IMPORT_NS(…);
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