// SPDX-License-Identifier: GPL-2.0 /* * Intel Lynxpoint PCH pinctrl/GPIO driver * * Copyright (c) 2012, 2019, Intel Corporation * Authors: Mathias Nyman <[email protected]> * Andy Shevchenko <[email protected]> */ #include <linux/acpi.h> #include <linux/array_size.h> #include <linux/bitops.h> #include <linux/cleanup.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/seq_file.h> #include <linux/slab.h> #include <linux/types.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include "pinctrl-intel.h" #define COMMUNITY(p, n) … static const struct pinctrl_pin_desc lptlp_pins[] = …; static const struct intel_community lptlp_communities[] = …; static const struct intel_pinctrl_soc_data lptlp_soc_data = …; /* LynxPoint chipset has support for 95 GPIO pins */ #define LP_NUM_GPIO … /* Bitmapped register offsets */ #define LP_ACPI_OWNED … #define LP_IRQ2IOXAPIC … #define LP_GC … #define LP_INT_STAT … #define LP_INT_ENABLE … /* Each pin has two 32 bit config registers, starting at 0x100 */ #define LP_CONFIG1 … #define LP_CONFIG2 … /* LP_CONFIG1 reg bits */ #define OUT_LVL_BIT … #define IN_LVL_BIT … #define TRIG_SEL_BIT … #define INT_INV_BIT … #define DIR_BIT … #define USE_SEL_MASK … #define USE_SEL_NATIVE … #define USE_SEL_GPIO … /* LP_CONFIG2 reg bits */ #define GPINDIS_BIT … #define GPIWP_MASK … #define GPIWP_NONE … #define GPIWP_DOWN … #define GPIWP_UP … /* * Lynxpoint gpios are controlled through both bitmapped registers and * per gpio specific registers. The bitmapped registers are in chunks of * 3 x 32bit registers to cover all 95 GPIOs * * per gpio specific registers consist of two 32bit registers per gpio * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of * 190 config registers. * * A simplified view of the register layout look like this: * * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 * ... * LP_INT_ENABLE[31:0] ... * LP_INT_ENABLE[63:32] ... * LP_INT_ENABLE[94:64] ... * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 * LP2_CONFIG1 (gpio 2) ... * LP2_CONFIG2 (gpio 2) ... * ... * LP94_CONFIG1 (gpio 94) ... * LP94_CONFIG2 (gpio 94) ... * * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. */ static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, int reg) { … } static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) { … } static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) { … } static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) { … } static const struct pinctrl_ops lptlp_pinctrl_ops = …; static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { … } static void lp_gpio_enable_input(void __iomem *reg) { … } static void lp_gpio_disable_input(void __iomem *reg) { … } static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) { … } static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) { … } static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) { … } static const struct pinmux_ops lptlp_pinmux_ops = …; static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { … } static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { … } static const struct pinconf_ops lptlp_pinconf_ops = …; static const struct pinctrl_desc lptlp_pinctrl_desc = …; static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) { … } static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { … } static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { … } static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { … } static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static void lp_gpio_irq_handler(struct irq_desc *desc) { … } static void lp_irq_ack(struct irq_data *d) { … } static void lp_irq_unmask(struct irq_data *d) { … } static void lp_irq_mask(struct irq_data *d) { … } static void lp_irq_enable(struct irq_data *d) { … } static void lp_irq_disable(struct irq_data *d) { … } static int lp_irq_set_type(struct irq_data *d, unsigned int type) { … } static const struct irq_chip lp_irqchip = …; static int lp_gpio_irq_init_hw(struct gpio_chip *chip) { … } static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) { … } static int lp_gpio_probe(struct platform_device *pdev) { … } static int lp_gpio_resume(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(lp_gpio_pm_ops, NULL, lp_gpio_resume); static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); static struct platform_driver lp_gpio_driver = …; static int __init lp_gpio_init(void) { … } subsys_initcall(lp_gpio_init); static void __exit lp_gpio_exit(void) { … } module_exit(lp_gpio_exit); MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …; MODULE_IMPORT_NS(…);
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