// SPDX-License-Identifier: GPL-2.0 /* * Intel pinctrl/GPIO core driver. * * Copyright (C) 2015, Intel Corporation * Authors: Mathias Nyman <[email protected]> * Mika Westerberg <[email protected]> */ #include <linux/acpi.h> #include <linux/cleanup.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/log2.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/seq_file.h> #include <linux/string_helpers.h> #include <linux/time.h> #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> #include <linux/platform_data/x86/pwm-lpss.h> #include "../core.h" #include "pinctrl-intel.h" /* Offset from regs */ #define REVID … #define REVID_SHIFT … #define REVID_MASK … #define CAPLIST … #define CAPLIST_ID_SHIFT … #define CAPLIST_ID_MASK … #define CAPLIST_ID_GPIO_HW_INFO … #define CAPLIST_ID_PWM … #define CAPLIST_ID_BLINK … #define CAPLIST_ID_EXP … #define CAPLIST_NEXT_SHIFT … #define CAPLIST_NEXT_MASK … #define PADBAR … #define PADOWN_BITS … #define PADOWN_SHIFT(p) … #define PADOWN_MASK(p) … #define PADOWN_GPP(p) … #define PWMC … /* Offset from pad_regs */ #define PADCFG0 … #define PADCFG0_RXEVCFG_MASK … #define PADCFG0_RXEVCFG_LEVEL … #define PADCFG0_RXEVCFG_EDGE … #define PADCFG0_RXEVCFG_DISABLED … #define PADCFG0_RXEVCFG_EDGE_BOTH … #define PADCFG0_PREGFRXSEL … #define PADCFG0_RXINV … #define PADCFG0_GPIROUTIOXAPIC … #define PADCFG0_GPIROUTSCI … #define PADCFG0_GPIROUTSMI … #define PADCFG0_GPIROUTNMI … #define PADCFG0_PMODE_SHIFT … #define PADCFG0_PMODE_MASK … #define PADCFG0_PMODE_GPIO … #define PADCFG0_GPIODIS_SHIFT … #define PADCFG0_GPIODIS_MASK … #define PADCFG0_GPIODIS_NONE … #define PADCFG0_GPIODIS_OUTPUT … #define PADCFG0_GPIODIS_INPUT … #define PADCFG0_GPIODIS_FULL … #define PADCFG0_GPIORXDIS … #define PADCFG0_GPIOTXDIS … #define PADCFG0_GPIORXSTATE … #define PADCFG0_GPIOTXSTATE … #define PADCFG1 … #define PADCFG1_TERM_UP … #define PADCFG1_TERM_SHIFT … #define PADCFG1_TERM_MASK … #define PADCFG1_TERM_20K … #define PADCFG1_TERM_5K … #define PADCFG1_TERM_4K … #define PADCFG1_TERM_1K … #define PADCFG1_TERM_952 … #define PADCFG1_TERM_833 … #define PADCFG1_TERM_800 … #define PADCFG2 … #define PADCFG2_DEBOUNCE_SHIFT … #define PADCFG2_DEBOUNCE_MASK … #define PADCFG2_DEBEN … #define DEBOUNCE_PERIOD_NSEC … struct intel_pad_context { … }; struct intel_community_context { … }; #define pin_to_padno(c, p) … #define padgroup_offset(g, p) … #define for_each_intel_pin_community(pctrl, community) … \ #define for_each_intel_community_pad_group(community, grp) … \ #define for_each_intel_pad_group(pctrl, community, grp) … #define for_each_intel_gpio_group(pctrl, community, grp) … const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl, unsigned int pin) { … } EXPORT_SYMBOL_NS_GPL(…); static const struct intel_padgroup * intel_community_get_padgroup(const struct intel_community *community, unsigned int pin) { … } static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int reg) { … } static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin) { … } static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin) { … } /** * enum - Locking variants of the pad configuration * @PAD_UNLOCKED: pad is fully controlled by the configuration registers * @PAD_LOCKED: pad configuration registers, except TX state, are locked * @PAD_LOCKED_TX: pad configuration TX state is locked * @PAD_LOCKED_FULL: pad configuration registers are locked completely * * Locking is considered as read-only mode for corresponding registers and * their respective fields. That said, TX state bit is locked separately from * the main locking scheme. */ enum { … }; static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin) { … } static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin) { … } static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin) { … } int intel_get_groups_count(struct pinctrl_dev *pctldev) { … } EXPORT_SYMBOL_NS_GPL(…); const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) { … } EXPORT_SYMBOL_NS_GPL(…); int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, const unsigned int **pins, unsigned int *npins) { … } EXPORT_SYMBOL_NS_GPL(…); static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin) { … } static const struct pinctrl_ops intel_pinctrl_ops = …; int intel_get_functions_count(struct pinctrl_dev *pctldev) { … } EXPORT_SYMBOL_NS_GPL(…); const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) { … } EXPORT_SYMBOL_NS_GPL(…); int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, const char * const **groups, unsigned int * const ngroups) { … } EXPORT_SYMBOL_NS_GPL(…); static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { … } /** * enum - Possible pad physical connections * @PAD_CONNECT_NONE: pad is fully disconnected * @PAD_CONNECT_INPUT: pad is in input only mode * @PAD_CONNECT_OUTPUT: pad is in output only mode * @PAD_CONNECT_FULL: pad is fully connected */ enum { … }; static int __intel_gpio_get_direction(u32 value) { … } static u32 __intel_gpio_set_direction(u32 value, bool input, bool output) { … } static int __intel_gpio_get_gpio_mode(u32 value) { … } static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) { … } static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) { … } static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) { … } static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) { … } static const struct pinmux_ops intel_pinmux_ops = …; static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 *arg) { … } static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 *arg) { … } static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 *arg) { … } static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { … } static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, unsigned long config) { … } static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin) { … } static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int debounce) { … } static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int nconfigs) { … } static const struct pinconf_ops intel_pinconf_ops = …; static const struct pinctrl_desc intel_pinctrl_desc = …; /** * intel_gpio_to_pin() - Translate from GPIO offset to pin number * @pctrl: Pinctrl structure * @offset: GPIO offset from gpiolib * @community: Community is filled here if not %NULL * @padgrp: Pad group is filled here if not %NULL * * When coming through gpiolib irqchip, the GPIO offset is not * automatically translated to pinctrl pin number. This function can be * used to find out the corresponding pinctrl pin. * * Return: a pin number and pointers to the community and pad group, which * the pin belongs to, or negative error code if translation can't be done. */ static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset, const struct intel_community **community, const struct intel_padgroup **padgrp) { … } /** * intel_pin_to_gpio() - Translate from pin number to GPIO offset * @pctrl: Pinctrl structure * @pin: pin number * * Translate the pin number of pinctrl to GPIO offset * * Return: a GPIO offset, or negative error code if translation can't be done. */ static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin) { … } static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) { … } static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { … } static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { … } static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { … } static const struct gpio_chip intel_gpio_chip = …; static void intel_gpio_irq_ack(struct irq_data *d) { … } static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) { … } static void intel_gpio_irq_mask(struct irq_data *d) { … } static void intel_gpio_irq_unmask(struct irq_data *d) { … } static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) { … } static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) { … } static const struct irq_chip intel_gpio_irq_chip = …; static irqreturn_t intel_gpio_irq(int irq, void *data) { … } static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) { … } static int intel_gpio_irq_init_hw(struct gpio_chip *gc) { … } static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) { … } static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) { … } static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) { … } static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, struct intel_community *community) { … } static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, struct intel_community *community) { … } static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) { … } static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, struct intel_community *community) { … } int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { … } EXPORT_SYMBOL_NS_GPL(…); int intel_pinctrl_probe_by_hid(struct platform_device *pdev) { … } EXPORT_SYMBOL_NS_GPL(…); int intel_pinctrl_probe_by_uid(struct platform_device *pdev) { … } EXPORT_SYMBOL_NS_GPL(…); const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) { … } EXPORT_SYMBOL_NS_GPL(…); static bool __intel_gpio_is_direct_irq(u32 value) { … } static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) { … } static int intel_pinctrl_suspend_noirq(struct device *dev) { … } static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) { … } static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, void __iomem *base, unsigned int gpp, u32 saved) { … } static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, void __iomem *base, unsigned int gpp, u32 saved) { … } static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int reg, u32 saved) { … } static int intel_pinctrl_resume_noirq(struct device *dev) { … } EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux