/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __INTEL_MG_PHY_REGS__ #define __INTEL_MG_PHY_REGS__ #include "intel_display_reg_defs.h" #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) … #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 … #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 … #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 … #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 … #define MG_TX1_LINK_PARAMS(ln, tc_port) … #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 … #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 … #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 … #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 … #define MG_TX2_LINK_PARAMS(ln, tc_port) … #define CRI_USE_FS32 … #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 … #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 … #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 … #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 … #define MG_TX1_PISO_READLOAD(ln, tc_port) … #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 … #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 … #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 … #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 … #define MG_TX2_PISO_READLOAD(ln, tc_port) … #define CRI_CALCINIT … #define MG_TX_SWINGCTRL_TX1LN0_PORT1 … #define MG_TX_SWINGCTRL_TX1LN1_PORT1 … #define MG_TX_SWINGCTRL_TX1LN0_PORT2 … #define MG_TX_SWINGCTRL_TX1LN1_PORT2 … #define MG_TX1_SWINGCTRL(ln, tc_port) … #define MG_TX_SWINGCTRL_TX2LN0_PORT1 … #define MG_TX_SWINGCTRL_TX2LN1_PORT1 … #define MG_TX_SWINGCTRL_TX2LN0_PORT2 … #define MG_TX_SWINGCTRL_TX2LN1_PORT2 … #define MG_TX2_SWINGCTRL(ln, tc_port) … #define CRI_TXDEEMPH_OVERRIDE_17_12(x) … #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK … #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 … #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 … #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 … #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 … #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 … #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 … #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 … #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 … #define MG_TX1_DRVCTRL(ln, tc_port) … #define MG_TX_DRVCTRL_TX2LN0_PORT1 … #define MG_TX_DRVCTRL_TX2LN1_PORT1 … #define MG_TX_DRVCTRL_TX2LN0_PORT2 … #define MG_TX_DRVCTRL_TX2LN1_PORT2 … #define MG_TX2_DRVCTRL(ln, tc_port) … #define CRI_TXDEEMPH_OVERRIDE_11_6(x) … #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK … #define CRI_TXDEEMPH_OVERRIDE_EN … #define CRI_TXDEEMPH_OVERRIDE_5_0(x) … #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK … #define CRI_LOADGEN_SEL(x) … #define CRI_LOADGEN_SEL_MASK … #define MG_CLKHUB_LN0_PORT1 … #define MG_CLKHUB_LN1_PORT1 … #define MG_CLKHUB_LN0_PORT2 … #define MG_CLKHUB_LN1_PORT2 … #define MG_CLKHUB(ln, tc_port) … #define CFG_LOW_RATE_LKREN_EN … #define MG_TX_DCC_TX1LN0_PORT1 … #define MG_TX_DCC_TX1LN1_PORT1 … #define MG_TX_DCC_TX1LN0_PORT2 … #define MG_TX_DCC_TX1LN1_PORT2 … #define MG_TX1_DCC(ln, tc_port) … #define MG_TX_DCC_TX2LN0_PORT1 … #define MG_TX_DCC_TX2LN1_PORT1 … #define MG_TX_DCC_TX2LN0_PORT2 … #define MG_TX_DCC_TX2LN1_PORT2 … #define MG_TX2_DCC(ln, tc_port) … #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) … #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK … #define CFG_AMI_CK_DIV_OVERRIDE_EN … #define MG_DP_MODE_LN0_ACU_PORT1 … #define MG_DP_MODE_LN1_ACU_PORT1 … #define MG_DP_MODE_LN0_ACU_PORT2 … #define MG_DP_MODE_LN1_ACU_PORT2 … #define MG_DP_MODE(ln, tc_port) … #define MG_DP_MODE_CFG_DP_X2_MODE … #define MG_DP_MODE_CFG_DP_X1_MODE … #define FIA1_BASE … #define FIA2_BASE … #define FIA3_BASE … #define _FIA(fia) … #define _MMIO_FIA(fia, off) … /* ICL PHY DFLEX registers */ #define PORT_TX_DFLEXDPMLE1(fia) … #define DFLEXDPMLE1_DPMLETC_MASK(idx) … #define DFLEXDPMLE1_DPMLETC_ML0(idx) … #define DFLEXDPMLE1_DPMLETC_ML1_0(idx) … #define DFLEXDPMLE1_DPMLETC_ML3(idx) … #define DFLEXDPMLE1_DPMLETC_ML3_2(idx) … #define DFLEXDPMLE1_DPMLETC_ML3_0(idx) … #define _MG_REFCLKIN_CTL_PORT1 … #define _MG_REFCLKIN_CTL_PORT2 … #define MG_REFCLKIN_CTL_OD_2_MUX(x) … #define MG_REFCLKIN_CTL_OD_2_MUX_MASK … #define MG_REFCLKIN_CTL(tc_port) … #define _MG_CLKTOP2_CORECLKCTL1_PORT1 … #define _MG_CLKTOP2_CORECLKCTL1_PORT2 … #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) … #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK … #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) … #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK … #define MG_CLKTOP2_CORECLKCTL1(tc_port) … #define _MG_CLKTOP2_HSCLKCTL_PORT1 … #define _MG_CLKTOP2_HSCLKCTL_PORT2 … #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) … #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK … #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) … #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK … #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK … #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 … #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 … #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 … #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 … #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) … #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT … #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK … #define MG_CLKTOP2_HSCLKCTL(tc_port) … #define _MG_PLL_DIV0_PORT1 … #define _MG_PLL_DIV0_PORT2 … #define MG_PLL_DIV0_FRACNEN_H … #define MG_PLL_DIV0_FBDIV_FRAC_MASK … #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT … #define MG_PLL_DIV0_FBDIV_FRAC(x) … #define MG_PLL_DIV0_FBDIV_INT_MASK … #define MG_PLL_DIV0_FBDIV_INT(x) … #define MG_PLL_DIV0(tc_port) … #define _MG_PLL_DIV1_PORT1 … #define _MG_PLL_DIV1_PORT2 … #define MG_PLL_DIV1_IREF_NDIVRATIO(x) … #define MG_PLL_DIV1_DITHER_DIV_1 … #define MG_PLL_DIV1_DITHER_DIV_2 … #define MG_PLL_DIV1_DITHER_DIV_4 … #define MG_PLL_DIV1_DITHER_DIV_8 … #define MG_PLL_DIV1_NDIVRATIO(x) … #define MG_PLL_DIV1_FBPREDIV_MASK … #define MG_PLL_DIV1_FBPREDIV(x) … #define MG_PLL_DIV1(tc_port) … #define _MG_PLL_LF_PORT1 … #define _MG_PLL_LF_PORT2 … #define MG_PLL_LF_TDCTARGETCNT(x) … #define MG_PLL_LF_AFCCNTSEL_256 … #define MG_PLL_LF_AFCCNTSEL_512 … #define MG_PLL_LF_GAINCTRL(x) … #define MG_PLL_LF_INT_COEFF(x) … #define MG_PLL_LF_PROP_COEFF(x) … #define MG_PLL_LF(tc_port) … #define _MG_PLL_FRAC_LOCK_PORT1 … #define _MG_PLL_FRAC_LOCK_PORT2 … #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 … #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 … #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) … #define MG_PLL_FRAC_LOCK_DCODITHEREN … #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN … #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) … #define MG_PLL_FRAC_LOCK(tc_port) … #define _MG_PLL_SSC_PORT1 … #define _MG_PLL_SSC_PORT2 … #define MG_PLL_SSC_EN … #define MG_PLL_SSC_TYPE(x) … #define MG_PLL_SSC_STEPLENGTH(x) … #define MG_PLL_SSC_STEPNUM(x) … #define MG_PLL_SSC_FLLEN … #define MG_PLL_SSC_STEPSIZE(x) … #define MG_PLL_SSC(tc_port) … #define _MG_PLL_BIAS_PORT1 … #define _MG_PLL_BIAS_PORT2 … #define MG_PLL_BIAS_BIAS_GB_SEL(x) … #define MG_PLL_BIAS_BIAS_GB_SEL_MASK … #define MG_PLL_BIAS_INIT_DCOAMP(x) … #define MG_PLL_BIAS_INIT_DCOAMP_MASK … #define MG_PLL_BIAS_BIAS_BONUS(x) … #define MG_PLL_BIAS_BIAS_BONUS_MASK … #define MG_PLL_BIAS_BIASCAL_EN … #define MG_PLL_BIAS_CTRIM(x) … #define MG_PLL_BIAS_CTRIM_MASK … #define MG_PLL_BIAS_VREF_RDAC(x) … #define MG_PLL_BIAS_VREF_RDAC_MASK … #define MG_PLL_BIAS_IREFTRIM(x) … #define MG_PLL_BIAS_IREFTRIM_MASK … #define MG_PLL_BIAS(tc_port) … #define _MG_PLL_TDC_COLDST_BIAS_PORT1 … #define _MG_PLL_TDC_COLDST_BIAS_PORT2 … #define MG_PLL_TDC_COLDST_IREFINT_EN … #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) … #define MG_PLL_TDC_COLDST_COLDSTART … #define MG_PLL_TDC_TDCOVCCORR_EN … #define MG_PLL_TDC_TDCSEL(x) … #define MG_PLL_TDC_COLDST_BIAS(tc_port) … #endif /* __INTEL_MG_PHY_REGS__ */
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