// SPDX-License-Identifier: MIT /* * Copyright © 2019 Intel Corporation * */ #include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" #include "intel_dsb_buffer.h" #include "intel_dsb_regs.h" #include "intel_vblank.h" #include "intel_vrr.h" #include "skl_watermark.h" #define CACHELINE_BYTES … struct intel_dsb { … }; /** * DOC: DSB * * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA * engine that can be programmed to download the DSB from memory. * It allows driver to batch submit display HW programming. This helps to * reduce loading time and CPU activity, thereby making the context switch * faster. DSB Support added from Gen12 Intel graphics based platform. * * DSB's can access only the pipe, plane, and transcoder Data Island Packet * registers. * * DSB HW can support only register writes (both indexed and direct MMIO * writes). There are no registers reads possible with DSB HW engine. */ /* DSB opcodes. */ #define DSB_OPCODE_SHIFT … #define DSB_OPCODE_NOOP … #define DSB_OPCODE_MMIO_WRITE … #define DSB_BYTE_EN … #define DSB_BYTE_EN_SHIFT … #define DSB_REG_VALUE_MASK … #define DSB_OPCODE_WAIT_USEC … #define DSB_OPCODE_WAIT_SCANLINE … #define DSB_OPCODE_WAIT_VBLANKS … #define DSB_OPCODE_WAIT_DSL_IN … #define DSB_OPCODE_WAIT_DSL_OUT … #define DSB_SCANLINE_UPPER_SHIFT … #define DSB_SCANLINE_LOWER_SHIFT … #define DSB_OPCODE_INTERRUPT … #define DSB_OPCODE_INDEXED_WRITE … /* see DSB_REG_VALUE_MASK */ #define DSB_OPCODE_POLL … /* see DSB_REG_VALUE_MASK */ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static const struct intel_crtc_state * pre_commit_crtc_state(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int dsb_vtotal(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int dsb_dewake_scanline_start(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int dsb_dewake_scanline_end(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int dsb_scanline_to_hw(struct intel_atomic_state *state, struct intel_crtc *crtc, int scanline) { … } static u32 dsb_chicken(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool assert_dsb_has_room(struct intel_dsb *dsb) { … } static void intel_dsb_dump(struct intel_dsb *dsb) { … } static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, enum intel_dsb_id dsb_id) { … } static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) { … } static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, u32 opcode, i915_reg_t reg) { … } static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) { … } static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) { … } /** * intel_dsb_reg_write() - Emit register wriite to the DSB context * @dsb: DSB context * @reg: register address. * @val: value. * * This function is used for writing register-value pair in command * buffer of DSB. */ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) { … } static u32 intel_dsb_mask_to_byte_en(u32 mask) { … } /* Note: mask implemented via byte enables! */ void intel_dsb_reg_write_masked(struct intel_dsb *dsb, i915_reg_t reg, u32 mask, u32 val) { … } void intel_dsb_noop(struct intel_dsb *dsb, int count) { … } void intel_dsb_nonpost_start(struct intel_dsb *dsb) { … } void intel_dsb_nonpost_end(struct intel_dsb *dsb) { … } static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb, u32 opcode, int lower, int upper) { … } static void intel_dsb_wait_dsl(struct intel_atomic_state *state, struct intel_dsb *dsb, int lower_in, int upper_in, int lower_out, int upper_out) { … } static void assert_dsl_ok(struct intel_atomic_state *state, struct intel_dsb *dsb, int start, int end) { … } void intel_dsb_wait_scanline_in(struct intel_atomic_state *state, struct intel_dsb *dsb, int start, int end) { … } void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, struct intel_dsb *dsb, int start, int end) { … } static void intel_dsb_align_tail(struct intel_dsb *dsb) { … } void intel_dsb_finish(struct intel_dsb *dsb) { … } static u32 dsb_error_int_status(struct intel_display *display) { … } static u32 dsb_error_int_en(struct intel_display *display) { … } static void _intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, u32 ctrl) { … } void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, bool wait_for_vblank) { … } static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, int hw_dewake_scanline) { … } /** * intel_dsb_commit() - Trigger workload execution of DSB. * @dsb: DSB context * @wait_for_vblank: wait for vblank before executing * * This function is used to do actual write to hardware using DSB. */ void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank) { … } void intel_dsb_wait(struct intel_dsb *dsb) { … } /** * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. * @state: the atomic state * @crtc: the CRTC * @dsb_id: the DSB engine to use * @max_cmds: number of commands we need to fit into command buffer * * This function prepare the command buffer which is used to store dsb * instructions with data. * * Returns: * DSB context, NULL on failure */ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds) { … } /** * intel_dsb_cleanup() - To cleanup DSB context. * @dsb: DSB context * * This function cleanup the DSB context by unpinning and releasing * the VMA object associated with it. */ void intel_dsb_cleanup(struct intel_dsb *dsb) { … } void intel_dsb_irq_handler(struct intel_display *display, enum pipe pipe, enum intel_dsb_id dsb_id) { … }
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