intel_dpll.c | Explore in Territory

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2020 Intel Corporation
 */

#include <linux/kernel.h>
#include <linux/string_helpers.h>

#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_cx0_phy.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
#include "intel_lvds.h"
#include "intel_lvds_regs.h"
#include "intel_panel.h"
#include "intel_pps.h"
#include "intel_snps_phy.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_sideband.h"

struct intel_dpll_funcs { … };

struct intel_limit { … };
static const struct intel_limit intel_limits_i8xx_dac = …;

static const struct intel_limit intel_limits_i8xx_dvo = …;

static const struct intel_limit intel_limits_i8xx_lvds = …;

static const struct intel_limit intel_limits_i9xx_sdvo = …;

static const struct intel_limit intel_limits_i9xx_lvds = …;


static const struct intel_limit intel_limits_g4x_sdvo = …;

static const struct intel_limit intel_limits_g4x_hdmi = …;

static const struct intel_limit intel_limits_g4x_single_channel_lvds = …;

static const struct intel_limit intel_limits_g4x_dual_channel_lvds = …;

static const struct intel_limit pnv_limits_sdvo = …;

static const struct intel_limit pnv_limits_lvds = …;

/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
static const struct intel_limit ilk_limits_dac = …;

static const struct intel_limit ilk_limits_single_lvds = …;

static const struct intel_limit ilk_limits_dual_lvds = …;

/* LVDS 100mhz refclk limits. */
static const struct intel_limit ilk_limits_single_lvds_100m = …;

static const struct intel_limit ilk_limits_dual_lvds_100m = …;

static const struct intel_limit intel_limits_vlv = …;

static const struct intel_limit intel_limits_chv = …;

static const struct intel_limit intel_limits_bxt = …;

/*
 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 * The helpers' return value is the rate of the clock that is fed to the
 * display engine's pipe which can be the above fast dot clock rate or a
 * divided-down version of it.
 */
/* m1 is reserved as 0 in Pineview, n is a ring counter */
static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
{ … }

static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
{ … }

int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
{ … }

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
{ … }

int chv_calc_dpll_params(int refclk, struct dpll *clock)
{ … }

static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state)
{ … }

void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
			    struct intel_dpll_hw_state *dpll_hw_state)
{ … }

/* Returns the clock of the currently programmed mode of the given pipe. */
void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state)
{ … }

void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
{ … }

void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
{ … }

/*
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */
static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
			       const struct intel_limit *limit,
			       const struct dpll *clock)
{ … }

static int
i9xx_select_p2_div(const struct intel_limit *limit,
		   const struct intel_crtc_state *crtc_state,
		   int target)
{ … }

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
static bool
i9xx_find_best_dpll(const struct intel_limit *limit,
		    struct intel_crtc_state *crtc_state,
		    int target, int refclk,
		    const struct dpll *match_clock,
		    struct dpll *best_clock)
{ … }

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
static bool
pnv_find_best_dpll(const struct intel_limit *limit,
		   struct intel_crtc_state *crtc_state,
		   int target, int refclk,
		   const struct dpll *match_clock,
		   struct dpll *best_clock)
{ … }

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
static bool
g4x_find_best_dpll(const struct intel_limit *limit,
		   struct intel_crtc_state *crtc_state,
		   int target, int refclk,
		   const struct dpll *match_clock,
		   struct dpll *best_clock)
{ … }

/*
 * Check if the calculated PLL configuration is more optimal compared to the
 * best configuration and error found so far. Return the calculated error.
 */
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
			       const struct dpll *calculated_clock,
			       const struct dpll *best_clock,
			       unsigned int best_error_ppm,
			       unsigned int *error_ppm)
{ … }

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.
 */
static bool
vlv_find_best_dpll(const struct intel_limit *limit,
		   struct intel_crtc_state *crtc_state,
		   int target, int refclk,
		   const struct dpll *match_clock,
		   struct dpll *best_clock)
{ … }

/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.
 */
static bool
chv_find_best_dpll(const struct intel_limit *limit,
		   struct intel_crtc_state *crtc_state,
		   int target, int refclk,
		   const struct dpll *match_clock,
		   struct dpll *best_clock)
{ … }

bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
			struct dpll *best_clock)
{ … }

u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
{ … }

static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
{ … }

static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state)
{ … }

static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state,
		     const struct dpll *clock,
		     const struct dpll *reduced_clock)
{ … }

static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
			      const struct dpll *clock,
			      const struct dpll *reduced_clock)
{ … }

static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state,
		     const struct dpll *clock,
		     const struct dpll *reduced_clock)
{ … }

static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
			      const struct dpll *clock,
			      const struct dpll *reduced_clock)
{ … }

static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
{ … }

static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
{ … }

static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
{ … }

static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)
{ … }

static u32 ilk_dpll(const struct intel_crtc_state *crtc_state,
		    const struct dpll *clock,
		    const struct dpll *reduced_clock)
{ … }

static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
			     const struct dpll *clock,
			     const struct dpll *reduced_clock)
{ … }

static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
{ … }

static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
{ … }

void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
{ … }

static u32 chv_dpll(const struct intel_crtc_state *crtc_state)
{ … }

void chv_compute_dpll(struct intel_crtc_state *crtc_state)
{ … }

static int chv_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
{ … }

static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
				   struct intel_crtc *crtc)
{ … }

static const struct intel_dpll_funcs mtl_dpll_funcs = …;

static const struct intel_dpll_funcs dg2_dpll_funcs = …;

static const struct intel_dpll_funcs hsw_dpll_funcs = …;

static const struct intel_dpll_funcs ilk_dpll_funcs = …;

static const struct intel_dpll_funcs chv_dpll_funcs = …;

static const struct intel_dpll_funcs vlv_dpll_funcs = …;

static const struct intel_dpll_funcs g4x_dpll_funcs = …;

static const struct intel_dpll_funcs pnv_dpll_funcs = …;

static const struct intel_dpll_funcs i9xx_dpll_funcs = …;

static const struct intel_dpll_funcs i8xx_dpll_funcs = …;

int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
{ … }

void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{ … }

static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
{ … }

void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
{ … }

static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
				 enum dpio_phy phy, enum dpio_channel ch)
{ … }

static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
{ … }

static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
{ … }

void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
{ … }

static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
{ … }

static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
{ … }

void chv_enable_pll(const struct intel_crtc_state *crtc_state)
{ … }

/**
 * vlv_force_pll_on - forcibly enable just the PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 * @dpll: PLL configuration
 *
 * Enable the PLL for @pipe using the supplied @dpll config. To be used
 * in cases where we need the PLL enabled even when @pipe is not going to
 * be enabled.
 */
int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
		     const struct dpll *dpll)
{ … }

void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{ … }

void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{ … }

void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
{ … }


/**
 * vlv_force_pll_off - forcibly disable just the PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe. To be used in cases where we need
 * the PLL enabled even when @pipe is not going to be enabled.
 */
void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
{ … }

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state)
{ … }

void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
{ … }

void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
{ … }
linux/drivers/gpu/drm/i915/display/intel_dpll.c
