/* * Copyright © 2006-2016 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include <linux/math.h> #include <linux/string_helpers.h> #include "bxt_dpio_phy_regs.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" #include "intel_dkl_phy_regs.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_dpll_mgr.h" #include "intel_hti.h" #include "intel_mg_phy_regs.h" #include "intel_pch_refclk.h" #include "intel_tc.h" /** * DOC: Display PLLs * * Display PLLs used for driving outputs vary by platform. While some have * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL * from a pool. In the latter scenario, it is possible that multiple pipes * share a PLL if their configurations match. * * This file provides an abstraction over display PLLs. The function * intel_shared_dpll_init() initializes the PLLs for the given platform. The * users of a PLL are tracked and that tracking is integrated with the atomic * modset interface. During an atomic operation, required PLLs can be reserved * for a given CRTC and encoder configuration by calling * intel_reserve_shared_dplls() and previously reserved PLLs can be released * with intel_release_shared_dplls(). * Changes to the users are first staged in the atomic state, and then made * effective by calling intel_shared_dpll_swap_state() during the atomic * commit phase. */ /* platform specific hooks for managing DPLLs */ struct intel_shared_dpll_funcs { … }; struct intel_dpll_mgr { … }; static void intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll_state *shared_dpll) { … } static struct intel_shared_dpll_state * intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) { … } /** * intel_get_shared_dpll_by_id - get a DPLL given its id * @i915: i915 device instance * @id: pll id * * Returns: * A pointer to the DPLL with @id */ struct intel_shared_dpll * intel_get_shared_dpll_by_id(struct drm_i915_private *i915, enum intel_dpll_id id) { … } /* For ILK+ */ void assert_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll, bool state) { … } static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) { … } enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) { … } static i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static i915_reg_t intel_tc_pll_enable_reg(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void _intel_enable_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void _intel_disable_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } /** * intel_enable_shared_dpll - enable a CRTC's shared DPLL * @crtc_state: CRTC, and its state, which has a shared DPLL * * Enable the shared DPLL used by @crtc. */ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) { … } /** * intel_disable_shared_dpll - disable a CRTC's shared DPLL * @crtc_state: CRTC, and its state, which has a shared DPLL * * Disable the shared DPLL used by @crtc. */ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) { … } static unsigned long intel_dpll_mask_all(struct drm_i915_private *i915) { … } static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_hw_state *dpll_hw_state, unsigned long dpll_mask) { … } /** * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is taken * @pll: DPLL for which the reference is taken * @shared_dpll_state: the DPLL atomic state in which the reference is tracked * * Take a reference for @pll tracking the use of it by @crtc. */ static void intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state) { … } static void intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } /** * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC * @crtc: CRTC on which behalf the reference is dropped * @pll: DPLL for which the reference is dropped * @shared_dpll_state: the DPLL atomic state in which the reference is tracked * * Drop a reference for @pll tracking the end of use of it by @crtc. */ void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state) { … } static void intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll) { … } static void intel_put_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } /** * intel_shared_dpll_swap_state - make atomic DPLL configuration effective * @state: atomic state * * This is the dpll version of drm_atomic_helper_swap_state() since the * helper does not handle driver-specific global state. * * For consistency with atomic helpers this function does a complete swap, * i.e. it also puts the current state into @state, even though there is no * need for that at this moment. */ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { … } static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) { … } static void ibx_pch_dpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void ibx_pch_dpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static int ibx_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int ibx_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static void ibx_dump_hw_state(struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { … } static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a, const struct intel_dpll_hw_state *_b) { … } static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = …; static const struct dpll_info pch_plls[] = …; static const struct intel_dpll_mgr pch_pll_mgr = …; static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void hsw_ddi_spll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void hsw_ddi_spll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } #define LC_FREQ … #define LC_FREQ_2K … #define P_MIN … #define P_MAX … #define P_INC … /* Constraints for PLL good behavior */ #define REF_MIN … #define REF_MAX … #define VCO_MIN … #define VCO_MAX … struct hsw_wrpll_rnp { … }; static unsigned hsw_wrpll_get_budget_for_freq(int clock) { … } static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget, unsigned int r2, unsigned int n2, unsigned int p, struct hsw_wrpll_rnp *best) { … } static void hsw_ddi_calculate_wrpll(int clock /* in Hz */, unsigned *r2_out, unsigned *n2_out, unsigned *p_out) { … } static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static struct intel_shared_dpll * hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) { … } static struct intel_shared_dpll * hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { … } static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static struct intel_shared_dpll * hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int hsw_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int hsw_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) { … } static void hsw_dump_hw_state(struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { … } static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a, const struct intel_dpll_hw_state *_b) { … } static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = …; static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = …; static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *hw_state) { … } static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = …; static const struct dpll_info hsw_plls[] = …; static const struct intel_dpll_mgr hsw_pll_mgr = …; struct skl_dpll_regs { … }; /* this array is indexed by the *shared* pll id */ static const struct skl_dpll_regs skl_dpll_regs[4] = …; static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct skl_dpll_hw_state *hw_state) { … } static void skl_ddi_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void skl_ddi_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } struct skl_wrpll_context { … }; /* DCO freq must be within +1%/-6% of the DCO central freq */ #define SKL_DCO_MAX_PDEVIATION … #define SKL_DCO_MAX_NDEVIATION … static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, u64 central_freq, u64 dco_freq, unsigned int divider) { … } static void skl_wrpll_get_multipliers(unsigned int p, unsigned int *p0 /* out */, unsigned int *p1 /* out */, unsigned int *p2 /* out */) { … } struct skl_wrpll_params { … }; static void skl_wrpll_params_populate(struct skl_wrpll_params *params, u64 afe_clock, int ref_clock, u64 central_freq, u32 p0, u32 p1, u32 p2) { … } static int skl_ddi_calculate_wrpll(int clock, int ref_clock, struct skl_wrpll_params *wrpll_params) { … } static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) { … } static int skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { … } static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int skl_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int skl_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) { … } static void skl_dump_hw_state(struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { … } static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a, const struct intel_dpll_hw_state *_b) { … } static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = …; static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = …; static const struct dpll_info skl_plls[] = …; static const struct intel_dpll_mgr skl_pll_mgr = …; static void bxt_ddi_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void bxt_ddi_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } /* pre-calculated values for DP linkrates */ static const struct dpll bxt_dp_clk_val[] = …; static int bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, struct dpll *clk_div) { … } static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, struct dpll *clk_div) { … } static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, const struct dpll *clk_div) { … } static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { … } static int bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { … } static int bxt_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int bxt_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) { … } static void bxt_dump_hw_state(struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { … } static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a, const struct intel_dpll_hw_state *_b) { … } static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = …; static const struct dpll_info bxt_plls[] = …; static const struct intel_dpll_mgr bxt_pll_mgr = …; static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv, int *qdiv, int *kdiv) { … } static void icl_wrpll_params_populate(struct skl_wrpll_params *params, u32 dco_freq, u32 ref_freq, int pdiv, int qdiv, int kdiv) { … } /* * Display WA #22010492432: ehl, tgl, adl-s, adl-p * Program half of the nominal DCO divider fraction value. */ static bool ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) { … } struct icl_combo_pll_params { … }; /* * These values alrea already adjusted: they're the bits we write to the * registers, not the logical values. */ static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = …; /* Also used for 38.4 MHz values. */ static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = …; static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = …; static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = …; static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = …; static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = …; static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { … } static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { … } static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static int icl_wrpll_ref_clock(struct drm_i915_private *i915) { … } static int icl_calc_wrpll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *wrpll_params) { … } static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void icl_calc_dpll_state(struct drm_i915_private *i915, const struct skl_wrpll_params *pll_params, struct intel_dpll_hw_state *dpll_hw_state) { … } static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, u32 *target_dco_khz, struct icl_dpll_hw_state *hw_state, bool is_dkl) { … } /* * The specification for this function uses real numbers, so the math had to be * adapted to integer-only calculation, that's why it looks so different. */ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *dpll_hw_state) { … } static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } /** * icl_set_active_port_dpll - select the active port DPLL for a given CRTC * @crtc_state: state for the CRTC to select the DPLL for * @port_dpll_id: the active @port_dpll_id to select * * Select the given @port_dpll_id instance from the DPLLs reserved for the * CRTC. */ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, enum icl_port_dpll_id port_dpll_id) { … } static void icl_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int icl_compute_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static int icl_get_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } static void icl_put_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } static bool mg_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static bool icl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state, i915_reg_t enable_reg) { … } static bool combo_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static void icl_dpll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) { … } static void icl_mg_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) { … } static void dkl_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) { … } static void icl_pll_power_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { … } static void icl_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { … } static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void combo_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void tbt_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void mg_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } static void icl_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { … } static void combo_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void tbt_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void mg_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) { … } static void icl_dump_hw_state(struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { … } static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a, const struct intel_dpll_hw_state *_b) { … } static const struct intel_shared_dpll_funcs combo_pll_funcs = …; static const struct intel_shared_dpll_funcs tbt_pll_funcs = …; static const struct intel_shared_dpll_funcs mg_pll_funcs = …; static const struct dpll_info icl_plls[] = …; static const struct intel_dpll_mgr icl_pll_mgr = …; static const struct dpll_info ehl_plls[] = …; static const struct intel_dpll_mgr ehl_pll_mgr = …; static const struct intel_shared_dpll_funcs dkl_pll_funcs = …; static const struct dpll_info tgl_plls[] = …; static const struct intel_dpll_mgr tgl_pll_mgr = …; static const struct dpll_info rkl_plls[] = …; static const struct intel_dpll_mgr rkl_pll_mgr = …; static const struct dpll_info dg1_plls[] = …; static const struct intel_dpll_mgr dg1_pll_mgr = …; static const struct dpll_info adls_plls[] = …; static const struct intel_dpll_mgr adls_pll_mgr = …; static const struct dpll_info adlp_plls[] = …; static const struct intel_dpll_mgr adlp_pll_mgr = …; /** * intel_shared_dpll_init - Initialize shared DPLLs * @i915: i915 device * * Initialize shared DPLLs for @i915. */ void intel_shared_dpll_init(struct drm_i915_private *i915) { … } /** * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination * @state: atomic state * @crtc: CRTC to compute DPLLs for * @encoder: encoder * * This function computes the DPLL state for the given CRTC and encoder. * * The new configuration in the atomic commit @state is made effective by * calling intel_shared_dpll_swap_state(). * * Returns: * 0 on success, negative error code on falure. */ int intel_compute_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } /** * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination * @state: atomic state * @crtc: CRTC to reserve DPLLs for * @encoder: encoder * * This function reserves all required DPLLs for the given CRTC and encoder * combination in the current atomic commit @state and the new @crtc atomic * state. * * The new configuration in the atomic commit @state is made effective by * calling intel_shared_dpll_swap_state(). * * The reserved DPLLs should be released by calling * intel_release_shared_dplls(). * * Returns: * 0 if all required DPLLs were successfully reserved, * negative error code otherwise. */ int intel_reserve_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } /** * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state * @state: atomic state * @crtc: crtc from which the DPLLs are to be released * * This function releases all DPLLs reserved by intel_reserve_shared_dplls() * from the current atomic commit @state and the old @crtc atomic state. * * The new configuration in the atomic commit @state is made effective by * calling intel_shared_dpll_swap_state(). */ void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } /** * intel_update_active_dpll - update the active DPLL for a CRTC/encoder * @state: atomic state * @crtc: the CRTC for which to update the active DPLL * @encoder: encoder determining the type of port DPLL * * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state, * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The * DPLL selected will be based on the current mode of the encoder's port. */ void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { … } /** * intel_dpll_get_freq - calculate the DPLL's output frequency * @i915: i915 device * @pll: DPLL for which to calculate the output frequency * @dpll_hw_state: DPLL state from which to calculate the output frequency * * Return the output frequency corresponding to @pll's passed in @dpll_hw_state. */ int intel_dpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { … } /** * intel_dpll_get_hw_state - readout the DPLL's hardware state * @i915: i915 device * @pll: DPLL for which to calculate the output frequency * @dpll_hw_state: DPLL's hardware state * * Read out @pll's hardware state into @dpll_hw_state. */ bool intel_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { … } static void readout_dpll_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } void intel_dpll_update_ref_clks(struct drm_i915_private *i915) { … } void intel_dpll_readout_hw_state(struct drm_i915_private *i915) { … } static void sanitize_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { … } void intel_dpll_sanitize_state(struct drm_i915_private *i915) { … } /** * intel_dpll_dump_hw_state - dump hw_state * @i915: i915 drm device * @p: where to print the state to * @dpll_hw_state: hw state to be dumped * * Dumo out the relevant values in @dpll_hw_state. */ void intel_dpll_dump_hw_state(struct drm_i915_private *i915, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { … } /** * intel_dpll_compare_hw_state - compare the two states * @i915: i915 drm device * @a: first DPLL hw state * @b: second DPLL hw state * * Compare DPLL hw states @a and @b. * * Returns: true if the states are equal, false if the differ */ bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b) { … } static void verify_single_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_crtc *crtc, const struct intel_crtc_state *new_crtc_state) { … } static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll, const struct intel_shared_dpll *new_pll) { … } void intel_shared_dpll_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { … } void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) { … }
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