/* * Copyright © 2014 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Daniel Vetter <[email protected]> * */ #include "i915_drv.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_fifo_underrun.h" #include "intel_pch_display.h" /** * DOC: fifo underrun handling * * The i915 driver checks for display fifo underruns using the interrupt signals * provided by the hardware. This is enabled by default and fairly useful to * debug display issues, especially watermark settings. * * If an underrun is detected this is logged into dmesg. To avoid flooding logs * and occupying the cpu underrun interrupts are disabled after the first * occurrence until the next modeset on a given pipe. * * Note that underrun detection on gmch platforms is a bit more ugly since there * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe * interrupt register). Also on some other platforms underrun interrupts are * shared, which means that if we detect an underrun we need to disable underrun * reporting on all pipes. * * The code also supports underrun detection on the PCH transcoder. */ static bool ivb_can_enable_err_int(struct drm_device *dev) { … } static bool cpt_can_enable_serr_int(struct drm_device *dev) { … } static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) { … } static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable, bool old) { … } static void ilk_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable) { … } static void ivb_check_fifo_underruns(struct intel_crtc *crtc) { … } static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable, bool old) { … } static u32 icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv) { … } static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable) { … } static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pch_transcoder, bool enable) { … } static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) { … } static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, enum pipe pch_transcoder, bool enable, bool old) { … } static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, enum pipe pipe, bool enable) { … } /** * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state * @dev_priv: i915 device instance * @pipe: (CPU) pipe to set state for * @enable: whether underruns should be reported or not * * This function sets the fifo underrun state for @pipe. It is used in the * modeset code to avoid false positives since on many platforms underruns are * expected when disabling or enabling the pipe. * * Notice that on some platforms disabling underrun reports for one pipe * disables for all due to shared interrupts. Actual reporting is still per-pipe * though. * * Returns the previous state of underrun reporting. */ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { … } /** * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state * @dev_priv: i915 device instance * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) * @enable: whether underruns should be reported or not * * This function makes us disable or enable PCH fifo underruns for a specific * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO * underrun reporting for one transcoder may also disable all the other PCH * error interruts for the other transcoders, due to the fact that there's just * one interrupt mask/enable bit for all the transcoders. * * Returns the previous state of underrun reporting. */ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, enum pipe pch_transcoder, bool enable) { … } /** * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt * @dev_priv: i915 device instance * @pipe: (CPU) pipe to set state for * * This handles a CPU fifo underrun interrupt, generating an underrun warning * into dmesg if underrun reporting is enabled and then disables the underrun * interrupt to avoid an irq storm. */ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { … } /** * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt * @dev_priv: i915 device instance * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) * * This handles a PCH fifo underrun interrupt, generating an underrun warning * into dmesg if underrun reporting is enabled and then disables the underrun * interrupt to avoid an irq storm. */ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, enum pipe pch_transcoder) { … } /** * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately * @dev_priv: i915 device instance * * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared * error interrupt may have been disabled, and so CPU fifo underruns won't * necessarily raise an interrupt, and on GMCH platforms where underruns never * raise an interrupt. */ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) { … } /** * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately * @dev_priv: i915 device instance * * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared * error interrupt may have been disabled, and so PCH fifo underruns won't * necessarily raise an interrupt. */ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) { … } void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915, struct intel_crtc *crtc, bool enable) { … }
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