/* * Copyright © 2009 * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Authors: * Daniel Vetter <[email protected]> * * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c */ #include <drm/drm_fourcc.h> #include "gem/i915_gem_internal.h" #include "gem/i915_gem_object_frontbuffer.h" #include "gem/i915_gem_pm.h" #include "gt/intel_gpu_commands.h" #include "gt/intel_ring.h" #include "i915_drv.h" #include "i915_reg.h" #include "intel_color_regs.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_frontbuffer.h" #include "intel_overlay.h" #include "intel_pci_config.h" /* Limits for overlay size. According to intel doc, the real limits are: * Y width: 4095, UV width (planar): 2047, Y height: 2047, * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use * the mininum of both. */ #define IMAGE_MAX_WIDTH … #define IMAGE_MAX_HEIGHT … /* on 830 and 845 these large limits result in the card hanging */ #define IMAGE_MAX_WIDTH_LEGACY … #define IMAGE_MAX_HEIGHT_LEGACY … /* overlay register definitions */ /* OCMD register */ #define OCMD_TILED_SURFACE … #define OCMD_MIRROR_MASK … #define OCMD_MIRROR_MODE … #define OCMD_MIRROR_HORIZONTAL … #define OCMD_MIRROR_VERTICAL … #define OCMD_MIRROR_BOTH … #define OCMD_BYTEORDER_MASK … #define OCMD_UV_SWAP … #define OCMD_Y_SWAP … #define OCMD_Y_AND_UV_SWAP … #define OCMD_SOURCE_FORMAT_MASK … #define OCMD_RGB_888 … #define OCMD_RGB_555 … #define OCMD_RGB_565 … #define OCMD_YUV_422_PACKED … #define OCMD_YUV_411_PACKED … #define OCMD_YUV_420_PLANAR … #define OCMD_YUV_422_PLANAR … #define OCMD_YUV_410_PLANAR … #define OCMD_TVSYNCFLIP_PARITY … #define OCMD_TVSYNCFLIP_ENABLE … #define OCMD_BUF_TYPE_MASK … #define OCMD_BUF_TYPE_FRAME … #define OCMD_BUF_TYPE_FIELD … #define OCMD_TEST_MODE … #define OCMD_BUFFER_SELECT … #define OCMD_BUFFER0 … #define OCMD_BUFFER1 … #define OCMD_FIELD_SELECT … #define OCMD_FIELD0 … #define OCMD_FIELD1 … #define OCMD_ENABLE … /* OCONFIG register */ #define OCONF_PIPE_MASK … #define OCONF_PIPE_A … #define OCONF_PIPE_B … #define OCONF_GAMMA2_ENABLE … #define OCONF_CSC_MODE_BT601 … #define OCONF_CSC_MODE_BT709 … #define OCONF_CSC_BYPASS … #define OCONF_CC_OUT_8BIT … #define OCONF_TEST_MODE … #define OCONF_THREE_LINE_BUFFER … #define OCONF_TWO_LINE_BUFFER … /* DCLRKM (dst-key) register */ #define DST_KEY_ENABLE … #define CLK_RGB24_MASK … #define CLK_RGB16_MASK … #define CLK_RGB15_MASK … #define RGB30_TO_COLORKEY(c) … #define RGB16_TO_COLORKEY(c) … #define RGB15_TO_COLORKEY(c) … #define RGB8I_TO_COLORKEY(c) … /* overlay flip addr flag */ #define OFC_UPDATE … /* polyphase filter coefficients */ #define N_HORIZ_Y_TAPS … #define N_VERT_Y_TAPS … #define N_HORIZ_UV_TAPS … #define N_VERT_UV_TAPS … #define N_PHASES … #define MAX_TAPS … /* memory bufferd overlay registers */ struct overlay_registers { … }; struct intel_overlay { … }; static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, bool enable) { … } static struct i915_request * alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) { … } /* overlay needs to be disable in OCMD reg */ static int intel_overlay_on(struct intel_overlay *overlay) { … } static void intel_overlay_flip_prepare(struct intel_overlay *overlay, struct i915_vma *vma) { … } /* overlay needs to be enabled in OCMD reg */ static int intel_overlay_continue(struct intel_overlay *overlay, struct i915_vma *vma, bool load_polyphase_filter) { … } static void intel_overlay_release_old_vma(struct intel_overlay *overlay) { … } static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) { … } static void intel_overlay_off_tail(struct intel_overlay *overlay) { … } static void intel_overlay_last_flip_retire(struct i915_active *active) { … } /* overlay needs to be disabled in OCMD reg */ static int intel_overlay_off(struct intel_overlay *overlay) { … } /* recover from an interruption due to a signal * We have to be careful not to repeat work forever an make forward progess. */ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) { … } /* Wait for pending overlay flip and release old frame. * Needs to be called before the overlay register are changed * via intel_overlay_(un)map_regs */ static int intel_overlay_release_old_vid(struct intel_overlay *overlay) { … } void intel_overlay_reset(struct drm_i915_private *dev_priv) { … } static int packed_depth_bytes(u32 format) { … } static int packed_width_bytes(u32 format, short width) { … } static int uv_hsubsampling(u32 format) { … } static int uv_vsubsampling(u32 format) { … } static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) { … } static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = …; static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = …; static void update_polyphase_filter(struct overlay_registers __iomem *regs) { … } static bool update_scaling_factors(struct intel_overlay *overlay, struct overlay_registers __iomem *regs, struct drm_intel_overlay_put_image *params) { … } static void update_colorkey(struct intel_overlay *overlay, struct overlay_registers __iomem *regs) { … } static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) { … } static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) { … } static int intel_overlay_do_put_image(struct intel_overlay *overlay, struct drm_i915_gem_object *new_bo, struct drm_intel_overlay_put_image *params) { … } int intel_overlay_switch_off(struct intel_overlay *overlay) { … } static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, struct intel_crtc *crtc) { … } static void update_pfit_vscale_ratio(struct intel_overlay *overlay) { … } static int check_overlay_dst(struct intel_overlay *overlay, struct drm_intel_overlay_put_image *rec) { … } static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) { … } static int check_overlay_src(struct drm_i915_private *dev_priv, struct drm_intel_overlay_put_image *rec, struct drm_i915_gem_object *new_bo) { … } int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { … } static void update_reg_attrs(struct intel_overlay *overlay, struct overlay_registers __iomem *regs) { … } static bool check_gamma_bounds(u32 gamma1, u32 gamma2) { … } static bool check_gamma5_errata(u32 gamma5) { … } static int check_gamma(struct drm_intel_overlay_attrs *attrs) { … } int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { … } static int get_registers(struct intel_overlay *overlay, bool use_phys) { … } void intel_overlay_setup(struct drm_i915_private *dev_priv) { … } void intel_overlay_cleanup(struct drm_i915_private *dev_priv) { … } #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) struct intel_overlay_error_state { … }; struct intel_overlay_error_state * intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) { … } void intel_overlay_print_error_state(struct drm_printer *p, struct intel_overlay_error_state *error) { … } #endif
Codebase Browser
linux