/* SPDX-License-Identifier: MIT * * Copyright © 2023 Intel Corporation */ #ifndef __INTEL_CX0_PHY_REGS_H__ #define __INTEL_CX0_PHY_REGS_H__ #include "i915_reg_defs.h" #include "intel_display_limits.h" /* * Wrapper macro to convert from port number to the index used in some of the * registers. For Display version 20 and above it converts the port number to a * single range, starting with the TC offsets. When used together with * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second * range. Example: * * PORT_TC1 -> PORT_TC1 * PORT_TC2 -> PORT_TC2 * PORT_TC3 -> PORT_TC3 * PORT_TC4 -> PORT_TC4 * PORT_A -> PORT_TC4 + 1 * PORT_B -> PORT_TC4 + 2 * ... */ #define __xe2lpd_port_idx(port) … #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A … #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B … #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 … #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 … #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) … #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) … #define XELPDP_PORT_M2P_TRANSACTION_PENDING … #define XELPDP_PORT_M2P_COMMAND_TYPE_MASK … #define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED … #define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED … #define XELPDP_PORT_M2P_COMMAND_READ … #define XELPDP_PORT_M2P_DATA_MASK … #define XELPDP_PORT_M2P_DATA(val) … #define XELPDP_PORT_M2P_TRANSACTION_RESET … #define XELPDP_PORT_M2P_ADDRESS_MASK … #define XELPDP_PORT_M2P_ADDRESS(val) … #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) … #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) … #define XELPDP_PORT_P2M_RESPONSE_READY … #define XELPDP_PORT_P2M_COMMAND_TYPE_MASK … #define XELPDP_PORT_P2M_COMMAND_READ_ACK … #define XELPDP_PORT_P2M_COMMAND_WRITE_ACK … #define XELPDP_PORT_P2M_DATA_MASK … #define XELPDP_PORT_P2M_DATA(val) … #define XELPDP_PORT_P2M_ERROR_SET … #define XELPDP_MSGBUS_TIMEOUT_SLOW … #define XELPDP_MSGBUS_TIMEOUT_FAST_US … #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US … #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US … #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US … #define XELPDP_PORT_RESET_START_TIMEOUT_US … #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US … #define XELPDP_PORT_RESET_END_TIMEOUT … #define XELPDP_REFCLK_ENABLE_TIMEOUT_US … #define _XELPDP_PORT_BUF_CTL1_LN0_A … #define _XELPDP_PORT_BUF_CTL1_LN0_B … #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 … #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 … #define _XELPDP_PORT_BUF_CTL1(idx) … #define XELPDP_PORT_BUF_CTL1(i915__, port) … #define XELPDP_PORT_BUF_D2D_LINK_ENABLE … #define XELPDP_PORT_BUF_D2D_LINK_STATE … #define XELPDP_PORT_BUF_SOC_PHY_READY … #define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK … #define XELPDP_PORT_BUF_PORT_DATA_10BIT … #define XELPDP_PORT_BUF_PORT_DATA_20BIT … #define XELPDP_PORT_BUF_PORT_DATA_40BIT … #define XELPDP_PORT_REVERSAL … #define XELPDP_PORT_BUF_IO_SELECT_TBT … #define XELPDP_PORT_BUF_PHY_IDLE … #define XELPDP_TC_PHY_OWNERSHIP … #define XELPDP_TCSS_POWER_REQUEST … #define XELPDP_TCSS_POWER_STATE … #define XELPDP_PORT_WIDTH_MASK … #define XELPDP_PORT_WIDTH(val) … #define _XELPDP_PORT_BUF_CTL2(idx) … #define XELPDP_PORT_BUF_CTL2(i915__, port) … #define XELPDP_LANE_PIPE_RESET(lane) … #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) … #define XELPDP_LANE_POWERDOWN_UPDATE(lane) … #define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK … #define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) … #define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK … #define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) … #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) … #define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK … #define XELPDP_POWER_STATE_READY_MASK … #define XELPDP_POWER_STATE_READY(val) … #define _XELPDP_PORT_BUF_CTL3(idx) … #define XELPDP_PORT_BUF_CTL3(i915__, port) … #define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK … #define XELPDP_PLL_LANE_STAGGERING_DELAY(val) … #define XELPDP_POWER_STATE_ACTIVE_MASK … #define XELPDP_POWER_STATE_ACTIVE(val) … #define CX0_P0_STATE_ACTIVE … #define CX0_P2_STATE_READY … #define CX0_P2PG_STATE_DISABLE … #define CX0_P4PG_STATE_DISABLE … #define CX0_P2_STATE_RESET … #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A … #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B … #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 … #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 … #define _XELPDP_PORT_MSGBUS_TIMER(port, lane) … #define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) … #define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT … #define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK … #define XELPDP_PORT_MSGBUS_TIMER_VAL … #define _XELPDP_PORT_CLOCK_CTL_A … #define _XELPDP_PORT_CLOCK_CTL_B … #define _XELPDP_PORT_CLOCK_CTL_USBC1 … #define _XELPDP_PORT_CLOCK_CTL_USBC2 … #define _XELPDP_PORT_CLOCK_CTL(idx) … #define XELPDP_PORT_CLOCK_CTL(i915__, port) … #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) … #define XELPDP_LANE_PCLK_PLL_ACK(lane) … #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) … #define XELPDP_LANE_PCLK_REFCLK_ACK(lane) … #define XELPDP_TBT_CLOCK_REQUEST … #define XELPDP_TBT_CLOCK_ACK … #define XELPDP_DDI_CLOCK_SELECT_MASK … #define XELPDP_DDI_CLOCK_SELECT(val) … #define XELPDP_DDI_CLOCK_SELECT_NONE … #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK … #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK … #define XELPDP_DDI_CLOCK_SELECT_TBT_162 … #define XELPDP_DDI_CLOCK_SELECT_TBT_270 … #define XELPDP_DDI_CLOCK_SELECT_TBT_540 … #define XELPDP_DDI_CLOCK_SELECT_TBT_810 … #define XELPDP_FORWARD_CLOCK_UNGATE … #define XELPDP_LANE1_PHY_CLOCK_SELECT … #define XELPDP_SSC_ENABLE_PLLA … #define XELPDP_SSC_ENABLE_PLLB … /* C10 Vendor Registers */ #define PHY_C10_VDR_PLL(idx) … #define C10_PLL0_FRACEN … #define C10_PLL3_MULTIPLIERH_MASK … #define C10_PLL15_TXCLKDIV_MASK … #define C10_PLL15_HDMIDIV_MASK … #define PHY_C10_VDR_CMN(idx) … #define C10_CMN0_REF_RANGE … #define C10_CMN0_REF_CLK_MPLLB_DIV … #define C10_CMN3_TXVBOOST_MASK … #define C10_CMN3_TXVBOOST(val) … #define PHY_C10_VDR_TX(idx) … #define C10_TX0_TX_MPLLB_SEL … #define C10_TX1_TERMCTL_MASK … #define C10_TX1_TERMCTL(val) … #define PHY_C10_VDR_CONTROL(idx) … #define C10_VDR_CTRL_MSGBUS_ACCESS … #define C10_VDR_CTRL_MASTER_LANE … #define C10_VDR_CTRL_UPDATE_CFG … #define PHY_C10_VDR_CUSTOM_WIDTH … #define C10_VDR_CUSTOM_WIDTH_MASK … #define C10_VDR_CUSTOM_WIDTH_8_10 … #define PHY_C10_VDR_OVRD … #define PHY_C10_VDR_OVRD_TX1 … #define PHY_C10_VDR_OVRD_TX2 … #define PHY_C10_VDR_PRE_OVRD_TX1 … #define C10_PHY_OVRD_LEVEL_MASK … #define C10_PHY_OVRD_LEVEL(val) … #define PHY_CX0_VDROVRD_CTL(lane, tx, control) … /* PIPE SPEC Defined Registers */ #define PHY_CX0_TX_CONTROL(tx, control) … #define CONTROL2_DISABLE_SINGLE_TX … /* C20 Registers */ #define PHY_C20_WR_ADDRESS_L … #define PHY_C20_WR_ADDRESS_H … #define PHY_C20_WR_DATA_L … #define PHY_C20_WR_DATA_H … #define PHY_C20_RD_ADDRESS_L … #define PHY_C20_RD_ADDRESS_H … #define PHY_C20_RD_DATA_L … #define PHY_C20_RD_DATA_H … #define PHY_C20_VDR_CUSTOM_SERDES_RATE … #define PHY_C20_VDR_HDMI_RATE … #define PHY_C20_CONTEXT_TOGGLE … #define PHY_C20_CUSTOM_SERDES_MASK … #define PHY_C20_CUSTOM_SERDES(val) … #define PHY_C20_VDR_CUSTOM_WIDTH … #define PHY_C20_CUSTOM_WIDTH_MASK … #define PHY_C20_CUSTOM_WIDTH(val) … #define _MTL_C20_A_TX_CNTX_CFG … #define _MTL_C20_B_TX_CNTX_CFG … #define _MTL_C20_A_CMN_CNTX_CFG … #define _MTL_C20_B_CMN_CNTX_CFG … #define _MTL_C20_A_MPLLA_CFG … #define _MTL_C20_B_MPLLA_CFG … #define _MTL_C20_A_MPLLB_CFG … #define _MTL_C20_B_MPLLB_CFG … #define _XE2HPD_C20_A_TX_CNTX_CFG … #define _XE2HPD_C20_B_TX_CNTX_CFG … #define _XE2HPD_C20_A_CMN_CNTX_CFG … #define _XE2HPD_C20_B_CMN_CNTX_CFG … #define _XE2HPD_C20_A_MPLLA_CFG … #define _XE2HPD_C20_B_MPLLA_CFG … #define _XE2HPD_C20_A_MPLLB_CFG … #define _XE2HPD_C20_B_MPLLB_CFG … #define _IS_XE2HPD_C20(i915) … #define PHY_C20_A_TX_CNTX_CFG(i915, idx) … #define PHY_C20_B_TX_CNTX_CFG(i915, idx) … #define C20_PHY_TX_RATE … #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) … #define PHY_C20_B_CMN_CNTX_CFG(i915, idx) … #define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) … #define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) … #define C20_MPLLA_FRACEN … #define C20_FB_CLK_DIV4_EN … #define C20_MPLLA_TX_CLK_DIV_MASK … #define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) … #define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) … #define C20_MPLLB_TX_CLK_DIV_MASK … #define C20_MPLLB_FRACEN … #define C20_REF_CLK_MPLLB_DIV_MASK … #define C20_MULTIPLIER_MASK … #define C20_PHY_USE_MPLLB … /* C20 Phy VSwing Masks */ #define C20_PHY_VSWING_PREEMPH_MASK … #define C20_PHY_VSWING_PREEMPH(val) … #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) … /* C20 HDMI computed pll definitions */ #define REFCLK_38_4_MHZ … #define CLOCK_4999MHZ … #define CLOCK_9999MHZ … #define DATARATE_3000000000 … #define DATARATE_3500000000 … #define DATARATE_4000000000 … #define MPLL_FRACN_DEN … #define SSC_UP_SPREAD … #define WORD_CLK_DIV … #define MPLL_TX_CLK_DIV(val) … #define MPLL_MULTIPLIER(val) … #define MPLLB_ANA_FREQ_VCO_0 … #define MPLLB_ANA_FREQ_VCO_1 … #define MPLLB_ANA_FREQ_VCO_2 … #define MPLLB_ANA_FREQ_VCO_3 … #define MPLLB_ANA_FREQ_VCO_MASK … #define MPLLB_ANA_FREQ_VCO(val) … #define MPLL_DIV_MULTIPLIER_MASK … #define MPLL_DIV_MULTIPLIER(val) … #define CAL_DAC_CODE_31 … #define CAL_DAC_CODE_MASK … #define CAL_DAC_CODE(val) … #define CP_INT_GS_28 … #define CP_INT_GS_MASK … #define CP_INT_GS(val) … #define CP_PROP_GS_30 … #define CP_PROP_GS_MASK … #define CP_PROP_GS(val) … #define CP_INT_6 … #define CP_INT_MASK … #define CP_INT(val) … #define CP_PROP_20 … #define CP_PROP_MASK … #define CP_PROP(val) … #define V2I_2 … #define V2I_MASK … #define V2I(val) … #define HDMI_DIV_1 … #define HDMI_DIV_MASK … #define HDMI_DIV(val) … #endif /* __INTEL_CX0_REG_DEFS_H__ */
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