linux/drivers/gpu/drm/i915/display/intel_wm.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2023 Intel Corporation
 */

#include "i915_drv.h"
#include "i9xx_wm.h"
#include "intel_display_types.h"
#include "intel_wm.h"
#include "skl_watermark.h"

/**
 * intel_update_watermarks - update FIFO watermark values based on current modes
 * @i915: i915 device
 *
 * Calculate watermark values for the various WM regs based on current mode
 * and plane configuration.
 *
 * There are several cases to deal with here:
 *   - normal (i.e. non-self-refresh)
 *   - self-refresh (SR) mode
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
 *   - lines are small relative to FIFO size (buffer can hold more than 2
 *     lines), so need to account for TLB latency
 *
 *   The normal calculation is:
 *     watermark = dotclock * bytes per pixel * latency
 *   where latency is platform & configuration dependent (we assume pessimal
 *   values here).
 *
 *   The SR calculation is:
 *     watermark = (trunc(latency/line time)+1) * surface width *
 *       bytes per pixel
 *   where
 *     line time = htotal / dotclock
 *     surface width = hdisplay for normal plane and 64 for cursor
 *   and latency is assumed to be high, as above.
 *
 * The final value programmed to the register should always be rounded up,
 * and include an extra 2 entries to account for clock crossings.
 *
 * We don't use the sprite, so we can ignore that.  And on Crestline we have
 * to set the non-SR watermarks to 8.
 */
void intel_update_watermarks(struct drm_i915_private *i915)
{ … }

int intel_compute_pipe_wm(struct intel_atomic_state *state,
			  struct intel_crtc *crtc)
{ … }

int intel_compute_intermediate_wm(struct intel_atomic_state *state,
				  struct intel_crtc *crtc)
{ … }

bool intel_initial_watermarks(struct intel_atomic_state *state,
			      struct intel_crtc *crtc)
{ … }

void intel_atomic_update_watermarks(struct intel_atomic_state *state,
				    struct intel_crtc *crtc)
{ … }

void intel_optimize_watermarks(struct intel_atomic_state *state,
			       struct intel_crtc *crtc)
{ … }

int intel_compute_global_watermarks(struct intel_atomic_state *state)
{ … }

void intel_wm_get_hw_state(struct drm_i915_private *i915)
{ … }

bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
			    const struct intel_plane_state *plane_state)
{ … }

void intel_print_wm_latency(struct drm_i915_private *dev_priv,
			    const char *name, const u16 wm[])
{ … }

void intel_wm_init(struct drm_i915_private *i915)
{ … }

static void wm_latency_show(struct seq_file *m, const u16 wm[8])
{ … }

static int pri_wm_latency_show(struct seq_file *m, void *data)
{ … }

static int spr_wm_latency_show(struct seq_file *m, void *data)
{ … }

static int cur_wm_latency_show(struct seq_file *m, void *data)
{ … }

static int pri_wm_latency_open(struct inode *inode, struct file *file)
{ … }

static int spr_wm_latency_open(struct inode *inode, struct file *file)
{ … }

static int cur_wm_latency_open(struct inode *inode, struct file *file)
{ … }

static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
				size_t len, loff_t *offp, u16 wm[8])
{ … }

static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{ … }

static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{ … }

static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{ … }

static const struct file_operations i915_pri_wm_latency_fops = …;

static const struct file_operations i915_spr_wm_latency_fops = …;

static const struct file_operations i915_cur_wm_latency_fops = …;

void intel_wm_debugfs_register(struct drm_i915_private *i915)
{ … }