/* * Copyright © 2006 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Eric Anholt <[email protected]> * Thomas Richter <[email protected]> * * Minor modifications (Dithering enable): * Thomas Richter <[email protected]> * */ #include "intel_display_types.h" #include "intel_dvo_dev.h" /* * register definitions for the i82807aa. * * Documentation on this chipset can be found in datasheet #29069001 at * intel.com. */ /* * VCH Revision & GMBus Base Addr */ #define VR00 … #define VR00_BASE_ADDRESS_MASK … /* * Functionality Enable */ #define VR01 … /* * Enable the panel fitter */ #define VR01_PANEL_FIT_ENABLE … /* * Enables the LCD display. * * This must not be set while VR01_DVO_BYPASS_ENABLE is set. */ #define VR01_LCD_ENABLE … /* Enables the DVO repeater. */ #define VR01_DVO_BYPASS_ENABLE … /* Enables the DVO clock */ #define VR01_DVO_ENABLE … /* Enable dithering for 18bpp panels. Not documented. */ #define VR01_DITHER_ENABLE … /* * LCD Interface Format */ #define VR10 … /* Enables LVDS output instead of CMOS */ #define VR10_LVDS_ENABLE … /* Enables 18-bit LVDS output. */ #define VR10_INTERFACE_1X18 … /* Enables 24-bit LVDS or CMOS output */ #define VR10_INTERFACE_1X24 … /* Enables 2x18-bit LVDS or CMOS output. */ #define VR10_INTERFACE_2X18 … /* Enables 2x24-bit LVDS output */ #define VR10_INTERFACE_2X24 … /* Mask that defines the depth of the pipeline */ #define VR10_INTERFACE_DEPTH_MASK … /* * VR20 LCD Horizontal Display Size */ #define VR20 … /* * LCD Vertical Display Size */ #define VR21 … /* * Panel power down status */ #define VR30 … /* Read only bit indicating that the panel is not in a safe poweroff state. */ #define VR30_PANEL_ON … #define VR40 … #define VR40_STALL_ENABLE … #define VR40_VERTICAL_INTERP_ENABLE … #define VR40_ENHANCED_PANEL_FITTING … #define VR40_HORIZONTAL_INTERP_ENABLE … #define VR40_AUTO_RATIO_ENABLE … #define VR40_CLOCK_GATING_ENABLE … /* * Panel Fitting Vertical Ratio * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 */ #define VR41 … /* * Panel Fitting Horizontal Ratio * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 */ #define VR42 … /* * Horizontal Image Size */ #define VR43 … /* VR80 GPIO 0 */ #define VR80 … #define VR81 … #define VR82 … #define VR83 … #define VR84 … #define VR85 … #define VR86 … #define VR87 … /* VR88 GPIO 8 */ #define VR88 … /* Graphics BIOS scratch 0 */ #define VR8E … #define VR8E_PANEL_TYPE_MASK … #define VR8E_PANEL_INTERFACE_CMOS … #define VR8E_PANEL_INTERFACE_LVDS … #define VR8E_FORCE_DEFAULT_PANEL … /* Graphics BIOS scratch 1 */ #define VR8F … #define VR8F_VCH_PRESENT … #define VR8F_DISPLAY_CONN … #define VR8F_POWER_MASK … #define VR8F_POWER_POS … /* Some Bios implementations do not restore the DVO state upon * resume from standby. Thus, this driver has to handle it * instead. The following list contains all registers that * require saving. */ static const u16 backup_addresses[] = …; struct ivch_priv { … }; static void ivch_dump_regs(struct intel_dvo_device *dvo); /* * Reads a register on the ivch. * * Each of the 256 registers are 16 bits long. */ static bool ivch_read(struct intel_dvo_device *dvo, int addr, u16 *data) { … } /* Writes a 16-bit register on the ivch */ static bool ivch_write(struct intel_dvo_device *dvo, int addr, u16 data) { … } /* Probes the given bus and target address for an ivch */ static bool ivch_init(struct intel_dvo_device *dvo, struct i2c_adapter *adapter) { … } static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) { … } static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, struct drm_display_mode *mode) { … } /* Restore the DVO registers after a resume * from RAM. Registers have been saved during * the initialization. */ static void ivch_reset(struct intel_dvo_device *dvo) { … } /* Sets the power state of the panel connected to the ivch */ static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) { … } static bool ivch_get_hw_state(struct intel_dvo_device *dvo) { … } static void ivch_mode_set(struct intel_dvo_device *dvo, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) { … } static void ivch_dump_regs(struct intel_dvo_device *dvo) { … } static void ivch_destroy(struct intel_dvo_device *dvo) { … } const struct intel_dvo_dev_ops ivch_ops = …;
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