intel_cx0_phy.c | Explore in Territory

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2023 Intel Corporation
 */

#include <linux/log2.h>
#include <linux/math64.h>
#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_hdmi.h"
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_tc.h"

#define MB_WRITE_COMMITTED …
#define MB_WRITE_UNCOMMITTED …

#define for_each_cx0_lane_in_mask(__lane_mask, __lane) …

#define INTEL_CX0_LANE0 …
#define INTEL_CX0_LANE1 …
#define INTEL_CX0_BOTH_LANES …

bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
{ … }

static int lane_mask_to_lane(u8 lane_mask)
{ … }

static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
{ … }

static void
assert_dc_off(struct drm_i915_private *i915)
{ … }

static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
{ … }

/*
 * Prepare HW for CX0 phy transactions.
 *
 * It is required that PSR and DC5/6 are disabled before any CX0 message
 * bus transaction is executed.
 *
 * We also do the msgbus timer programming here to ensure that the timer
 * is already programmed before any access to the msgbus.
 */
static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
{ … }

static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
{ … }

static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
					    int lane)
{ … }

static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
{ … }

static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
				  int command, int lane, u32 *val)
{ … }

static int __intel_cx0_read_once(struct intel_encoder *encoder,
				 int lane, u16 addr)
{ … }

static u8 __intel_cx0_read(struct intel_encoder *encoder,
			   int lane, u16 addr)
{ … }

static u8 intel_cx0_read(struct intel_encoder *encoder,
			 u8 lane_mask, u16 addr)
{ … }

static int __intel_cx0_write_once(struct intel_encoder *encoder,
				  int lane, u16 addr, u8 data, bool committed)
{ … }

static void __intel_cx0_write(struct intel_encoder *encoder,
			      int lane, u16 addr, u8 data, bool committed)
{ … }

static void intel_cx0_write(struct intel_encoder *encoder,
			    u8 lane_mask, u16 addr, u8 data, bool committed)
{ … }

static void intel_c20_sram_write(struct intel_encoder *encoder,
				 int lane, u16 addr, u16 data)
{ … }

static u16 intel_c20_sram_read(struct intel_encoder *encoder,
			       int lane, u16 addr)
{ … }

static void __intel_cx0_rmw(struct intel_encoder *encoder,
			    int lane, u16 addr, u8 clear, u8 set, bool committed)
{ … }

static void intel_cx0_rmw(struct intel_encoder *encoder,
			  u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
{ … }

static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state)
{ … }

static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
{ … }

void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
				     const struct intel_crtc_state *crtc_state)
{ … }

/*
 * Basic DP link rates with 38.4 MHz reference clock.
 * Note: The tables below are with SSC. In non-ssc
 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
 * programmed 0.
 */

static const struct intel_c10pll_state mtl_c10_dp_rbr = …;

static const struct intel_c10pll_state mtl_c10_edp_r216 = …;

static const struct intel_c10pll_state mtl_c10_edp_r243 = …;

static const struct intel_c10pll_state mtl_c10_dp_hbr1 = …;

static const struct intel_c10pll_state mtl_c10_edp_r324 = …;

static const struct intel_c10pll_state mtl_c10_edp_r432 = …;

static const struct intel_c10pll_state mtl_c10_dp_hbr2 = …;

static const struct intel_c10pll_state mtl_c10_edp_r675 = …;

static const struct intel_c10pll_state mtl_c10_dp_hbr3 = …;

static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = …;

static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = …;

/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = …;

static const struct intel_c20pll_state mtl_c20_dp_hbr1 = …;

static const struct intel_c20pll_state mtl_c20_dp_hbr2 = …;

static const struct intel_c20pll_state mtl_c20_dp_hbr3 = …;

/* C20 basic DP 2.0 tables */
static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = …;

static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = …;

static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = …;

static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = …;

/*
 * eDP link rates with 38.4 MHz reference clock.
 */

static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = …;

static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = …;

static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = …;

static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = …;

static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = …;

static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = …;

static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = …;

static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = …;

/*
 * HDMI link rates with 38.4 MHz reference clock.
 */

static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_594 = …;

/* Precomputed C10 HDMI PLL tables */
static const struct intel_c10pll_state mtl_c10_hdmi_27027 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_28320 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_30240 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_31500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_36000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_40000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_49500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_50000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_57284 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_58000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_65000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_71000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_74176 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_75000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_78750 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_85500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_88750 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_106500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_108000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_115500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_119000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_135000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_138500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_147160 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_148352 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_154000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_162000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_167000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_197802 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_198000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_209800 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_241500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_262750 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_268500 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_296703 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_297000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_319750 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_497750 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_592000 = …;

static const struct intel_c10pll_state mtl_c10_hdmi_593407 = …;

static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = …;

static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_594 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_300 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_600 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_800 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_1000 = …;

static const struct intel_c20pll_state mtl_c20_hdmi_1200 = …;

static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = …;

static int intel_c10_phy_check_hdmi_link_rate(int clock)
{ … }

static const struct intel_c10pll_state * const *
intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
			struct intel_encoder *encoder)
{ … }

static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
				    struct intel_encoder *encoder)
{ … }

static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
				   struct intel_encoder *encoder)
{ … }

static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
					  struct intel_c10pll_state *pll_state)
{ … }

static void intel_c10_pll_program(struct drm_i915_private *i915,
				  const struct intel_crtc_state *crtc_state,
				  struct intel_encoder *encoder)
{ … }

static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
				       const struct intel_c10pll_state *hw_state)
{ … }

static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state)
{ … }

static int intel_c20_phy_check_hdmi_link_rate(int clock)
{ … }

int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
{ … }

static const struct intel_c20pll_state * const *
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
			 struct intel_encoder *encoder)
{ … }

static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
				   struct intel_encoder *encoder)
{ … }

int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
			    struct intel_encoder *encoder)
{ … }

static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
{ … }

static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
					const struct intel_c20pll_state *pll_state)
{ … }

static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
					  struct intel_c20pll_state *pll_state)
{ … }

static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
				       const struct intel_c20pll_state *hw_state)
{ … }

void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
				const struct intel_cx0pll_state *hw_state)
{ … }

static u8 intel_c20_get_dp_rate(u32 clock)
{ … }

static u8 intel_c20_get_hdmi_rate(u32 clock)
{ … }

static bool is_dp2(u32 clock)
{ … }

static bool is_hdmi_frl(u32 clock)
{ … }

static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
{ … }

static int intel_get_c20_custom_width(u32 clock, bool dp)
{ … }

static void intel_c20_pll_program(struct drm_i915_private *i915,
				  const struct intel_crtc_state *crtc_state,
				  struct intel_encoder *encoder)
{ … }

static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
					const struct intel_c10pll_state *pll_state)
{ … }

static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
					 const struct intel_crtc_state *crtc_state,
					 bool lane_reversal)
{ … }

static u32 intel_cx0_get_powerdown_update(u8 lane_mask)
{ … }

static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
{ … }

static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
						u8 lane_mask, u8 state)
{ … }

static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
{ … }

static u32 intel_cx0_get_pclk_refclk_request(u8 lane_mask)
{ … }

static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)
{ … }

static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
				     bool lane_reversal)
{ … }

static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
				       struct intel_encoder *encoder, int lane_count,
				       bool lane_reversal)
{ … }

static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)
{ … }

static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
{ … }

static void intel_cx0pll_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state)
{ … }

int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
{ … }

static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
{ … }

static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
				     const struct intel_crtc_state *crtc_state)
{ … }

void intel_mtl_pll_enable(struct intel_encoder *encoder,
			  const struct intel_crtc_state *crtc_state)
{ … }

static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
{ … }

static void intel_cx0pll_disable(struct intel_encoder *encoder)
{ … }

static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
{ … }

void intel_mtl_pll_disable(struct intel_encoder *encoder)
{ … }

enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
			const struct intel_crtc_state *crtc_state)
{ … }

static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
				      struct intel_crtc *crtc,
				      struct intel_encoder *encoder,
				      struct intel_c10pll_state *mpllb_hw_state)
{ … }

void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
				   struct intel_cx0pll_state *pll_state)
{ … }

static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
				     const struct intel_c10pll_state *b)
{ … }

static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a,
				     const struct intel_c20pll_state *b)
{ … }

bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
				   const struct intel_cx0pll_state *b)
{ … }

int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
				 const struct intel_cx0pll_state *pll_state)
{ … }

static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
				      struct intel_crtc *crtc,
				      struct intel_encoder *encoder,
				      struct intel_c20pll_state *mpll_hw_state)
{ … }

void intel_cx0pll_state_verify(struct intel_atomic_state *state,
			       struct intel_crtc *crtc)
{ … }
linux/drivers/gpu/drm/i915/display/intel_cx0_phy.c
