/* * Copyright © 2008 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * Authors: * Keith Packard <[email protected]> * */ #include <linux/export.h> #include <linux/i2c.h> #include <linux/notifier.h> #include <linux/slab.h> #include <linux/sort.h> #include <linux/string_helpers.h> #include <linux/timekeeping.h> #include <linux/types.h> #include <asm/byteorder.h> #include <drm/display/drm_dp_helper.h> #include <drm/display/drm_dp_tunnel.h> #include <drm/display/drm_dsc_helper.h> #include <drm/display/drm_hdmi_helper.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> #include <drm/drm_fixed.h> #include <drm/drm_probe_helper.h> #include "g4x_dp.h" #include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" #include "intel_alpm.h" #include "intel_atomic.h" #include "intel_audio.h" #include "intel_backlight.h" #include "intel_combo_phy_regs.h" #include "intel_connector.h" #include "intel_crtc.h" #include "intel_cx0_phy.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_aux.h" #include "intel_dp_hdcp.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" #include "intel_dp_tunnel.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_drrs.h" #include "intel_encoder.h" #include "intel_fifo_underrun.h" #include "intel_hdcp.h" #include "intel_hdmi.h" #include "intel_hotplug.h" #include "intel_hotplug_irq.h" #include "intel_lspcon.h" #include "intel_lvds.h" #include "intel_modeset_lock.h" #include "intel_panel.h" #include "intel_pch_display.h" #include "intel_pps.h" #include "intel_psr.h" #include "intel_quirks.h" #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vrr.h" #include "intel_crtc_state_dump.h" #define dp_to_i915(__intel_dp) … /* DP DSC throughput values used for slice count calculations KPixels/s */ #define DP_DSC_PEAK_PIXEL_RATE … #define DP_DSC_MAX_ENC_THROUGHPUT_0 … #define DP_DSC_MAX_ENC_THROUGHPUT_1 … /* Max DSC line buffer depth supported by HW. */ #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH … /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ #define DP_DSC_FEC_OVERHEAD_FACTOR … /* Compliance test status bits */ #define INTEL_DP_RESOLUTION_SHIFT_MASK … #define INTEL_DP_RESOLUTION_PREFERRED … #define INTEL_DP_RESOLUTION_STANDARD … #define INTEL_DP_RESOLUTION_FAILSAFE … /* Constants for DP DSC configurations */ static const u8 valid_dsc_bpp[] = …; /* With Single pipe configuration, HW is capable of supporting maximum * of 4 slices per line. */ static const u8 valid_dsc_slicecount[] = …; /** * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct * * If a CPU or PCH DP output is attached to an eDP panel, this function * will return true, and false otherwise. * * This function is not safe to use prior to encoder type being set. */ bool intel_dp_is_edp(struct intel_dp *intel_dp) { … } static void intel_dp_unset_edid(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) { … } /** * intel_dp_link_symbol_size - get the link symbol size for a given link rate * @rate: link rate in 10kbit/s units * * Returns the link symbol size in bits/symbol units depending on the link * rate -> channel coding. */ int intel_dp_link_symbol_size(int rate) { … } /** * intel_dp_link_symbol_clock - convert link rate to link symbol clock * @rate: link rate in 10kbit/s units * * Returns the link symbol clock frequency in kHz units depending on the * link rate and channel coding. */ int intel_dp_link_symbol_clock(int rate) { … } static int max_dprx_rate(struct intel_dp *intel_dp) { … } static int max_dprx_lane_count(struct intel_dp *intel_dp) { … } static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) { … } /* update sink rates from dpcd */ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) { … } static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) { … } static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) { … } static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) { … } /* Get length of rates array potentially limited by max_rate. */ static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) { … } /* Get length of common rates array potentially limited by max_rate. */ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, int max_rate) { … } int intel_dp_common_rate(struct intel_dp *intel_dp, int index) { … } /* Theoretical max between source and sink */ int intel_dp_max_common_rate(struct intel_dp *intel_dp) { … } int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) { … } /* Theoretical max between source and sink */ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) { … } static int forced_lane_count(struct intel_dp *intel_dp) { … } int intel_dp_max_lane_count(struct intel_dp *intel_dp) { … } static int intel_dp_min_lane_count(struct intel_dp *intel_dp) { … } /* * The required data bandwidth for a mode with given pixel clock and bpp. This * is the required net bandwidth independent of the data bandwidth efficiency. * * TODO: check if callers of this functions should use * intel_dp_effective_data_rate() instead. */ int intel_dp_link_required(int pixel_clock, int bpp) { … } /** * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead * @pixel_clock: pixel clock in kHz * @bpp_x16: bits per pixel .4 fixed point format * @bw_overhead: BW allocation overhead in 1ppm units * * Return the effective pixel data rate in kB/sec units taking into account * the provided SSC, FEC, DSC BW allocation overhead. */ int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, int bw_overhead) { … } /** * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params * @intel_dp: Intel DP object * @max_dprx_rate: Maximum data rate of the DPRX * @max_dprx_lanes: Maximum lane count of the DPRX * * Calculate the maximum data rate for the provided link parameters taking into * account any BW limitations by a DP tunnel attached to @intel_dp. * * Returns the maximum data rate in kBps units. */ int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, int max_dprx_rate, int max_dprx_lanes) { … } bool intel_dp_has_joiner(struct intel_dp *intel_dp) { … } static int dg2_max_source_rate(struct intel_dp *intel_dp) { … } static int icl_max_source_rate(struct intel_dp *intel_dp) { … } static int ehl_max_source_rate(struct intel_dp *intel_dp) { … } static int mtl_max_source_rate(struct intel_dp *intel_dp) { … } static int vbt_max_link_rate(struct intel_dp *intel_dp) { … } static void intel_dp_set_source_rates(struct intel_dp *intel_dp) { … } static int intersect_rates(const int *source_rates, int source_len, const int *sink_rates, int sink_len, int *common_rates) { … } /* return index of rate in rates array, or -1 if not found */ int intel_dp_rate_index(const int *rates, int len, int rate) { … } static int intel_dp_link_config_rate(struct intel_dp *intel_dp, const struct intel_dp_link_config *lc) { … } static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) { … } static int intel_dp_link_config_bw(struct intel_dp *intel_dp, const struct intel_dp_link_config *lc) { … } static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) { … } static void intel_dp_link_config_init(struct intel_dp *intel_dp) { … } void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) { … } int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) { … } static void intel_dp_set_common_rates(struct intel_dp *intel_dp) { … } static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, u8 lane_count) { … } u32 intel_dp_mode_to_fec_clock(u32 mode_clock) { … } int intel_dp_bw_fec_overhead(bool fec_enabled) { … } static int small_joiner_ram_size_bits(struct drm_i915_private *i915) { … } u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) { … } static u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner) { … } u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots) { … } u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, bool bigjoiner) { … } static bool source_can_output(struct intel_dp *intel_dp, enum intel_output_format format) { … } static bool dfp_can_convert_from_rgb(struct intel_dp *intel_dp, enum intel_output_format sink_format) { … } static bool dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, enum intel_output_format sink_format) { … } static bool dfp_can_convert(struct intel_dp *intel_dp, enum intel_output_format output_format, enum intel_output_format sink_format) { … } static enum intel_output_format intel_dp_output_format(struct intel_connector *connector, enum intel_output_format sink_format) { … } int intel_dp_min_bpp(enum intel_output_format output_format) { … } int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) { … } static enum intel_output_format intel_dp_sink_format(struct intel_connector *connector, const struct drm_display_mode *mode) { … } static int intel_dp_mode_min_output_bpp(struct intel_connector *connector, const struct drm_display_mode *mode) { … } static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, int hdisplay) { … } static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) { … } static enum drm_mode_status intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, int clock, int bpc, enum intel_output_format sink_format, bool respect_downstream_limits) { … } static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, int target_clock) { … } bool intel_dp_need_joiner(struct intel_dp *intel_dp, struct intel_connector *connector, int hdisplay, int clock) { … } bool intel_dp_has_dsc(const struct intel_connector *connector) { … } static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *_connector, struct drm_display_mode *mode) { … } bool intel_dp_source_supports_tps3(struct drm_i915_private *i915) { … } bool intel_dp_source_supports_tps4(struct drm_i915_private *i915) { … } static void snprintf_int_array(char *str, size_t len, const int *array, int nelem) { … } static void intel_dp_print_rates(struct intel_dp *intel_dp) { … } static int forced_link_rate(struct intel_dp *intel_dp) { … } int intel_dp_max_link_rate(struct intel_dp *intel_dp) { … } static int intel_dp_min_link_rate(struct intel_dp *intel_dp) { … } int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) { … } void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select) { … } bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) { … } static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, const struct intel_crtc_state *pipe_config) { … } bool intel_dp_supports_fec(struct intel_dp *intel_dp, const struct intel_connector *connector, const struct intel_crtc_state *pipe_config) { … } bool intel_dp_supports_dsc(const struct intel_connector *connector, const struct intel_crtc_state *crtc_state) { … } static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int bpc, bool respect_downstream_limits) { … } static int intel_dp_max_bpp(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, bool respect_downstream_limits) { … } /* Adjust link config limits based on compliance test requests. */ void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits) { … } static bool has_seamless_m_n(struct intel_connector *connector) { … } static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } /* Optimize link config in order: max bpp, min clock, min lanes */ static int intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state, const struct link_config_limits *limits) { … } static u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) { … } int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, u8 max_req_bpc) { … } static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915) { … } static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { … } static int intel_dp_get_slice_height(int vactive) { … } static int intel_dp_dsc_compute_params(const struct intel_connector *connector, struct intel_crtc_state *crtc_state) { … } static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, enum intel_output_format output_format) { … } static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, u32 lane_count, u32 mode_clock, enum intel_output_format output_format, int timeslots) { … } static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, u16 compressed_bppx16, int timeslots) { … } static u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, struct intel_crtc_state *pipe_config, int bpc) { … } int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) { … } int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, struct intel_crtc_state *pipe_config, int bpc) { … } static int dsc_src_min_compressed_bpp(void) { … } static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) { … } /* * From a list of valid compressed bpps try different compressed bpp and find a * suitable link configuration that can support it. */ static int icl_dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int dsc_max_bpp, int dsc_min_bpp, int pipe_bpp, int timeslots) { … } /* * From XE_LPD onwards we supports compression bpps in steps of 1 up to * uncompressed bpp-1. So we start from max compressed bpp and see if any * link configuration is able to support that compressed bpp, if not we * step down and check for lower compressed bpp. */ static int xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, const struct intel_connector *connector, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int dsc_max_bpp, int dsc_min_bpp, int pipe_bpp, int timeslots) { … } static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, const struct intel_connector *connector, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int pipe_bpp, int timeslots) { … } static u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) { … } static bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, struct drm_connector_state *conn_state, struct link_config_limits *limits, int pipe_bpp) { … } static int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, struct drm_connector_state *conn_state, struct link_config_limits *limits) { … } static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits, int timeslots) { … } static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits) { … } int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, struct link_config_limits *limits, int timeslots, bool compute_pipe_bpp) { … } /** * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits * @intel_dp: intel DP * @crtc_state: crtc state * @dsc: DSC compression mode * @limits: link configuration limits * * Calculates the output link min, max bpp values in @limits based on the * pipe bpp range, @crtc_state and @dsc mode. * * Returns %true in case of success. */ bool intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, bool dsc, struct link_config_limits *limits) { … } static bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, bool respect_downstream_limits, bool dsc, struct link_config_limits *limits) { … } int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) { … } bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915, bool use_joiner) { … } static int intel_dp_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, bool respect_downstream_limits) { … } bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, enum port port) { … } static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, struct drm_dp_vsc_sdp *vsc) { … } static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { … } static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } static void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } static bool can_enable_drrs(struct intel_connector *connector, const struct intel_crtc_state *pipe_config, const struct drm_display_mode *downclock_mode) { … } static void intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_crtc_state *pipe_config, int link_bpp_x16) { … } static bool intel_dp_has_audio(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { … } static int intel_dp_compute_output_format(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state, bool respect_downstream_limits) { … } void intel_dp_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { … } static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) { … } void intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { … } int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { … } void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, int lane_count) { … } void intel_dp_reset_link_params(struct intel_dp *intel_dp) { … } /* Enable backlight PWM and backlight PP control. */ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } /* Disable backlight PP control and backlight PWM. */ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) { … } static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) { … } static int write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) { … } static void intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, bool enable) { … } static void intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, bool enable) { … } static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, const struct intel_connector *connector, bool for_get_ref) { … } static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, struct intel_connector *connector) { … } static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, struct intel_connector *connector) { … } /** * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device * @state: atomic state * @connector: connector to enable the decompression for * @new_crtc_state: new state for the CRTC driving @connector * * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD * register of the appropriate sink/branch device. On SST this is always the * sink device, whereas on MST based on each device's DSC capabilities it's * either the last branch device (enabling decompression in it) or both the * last branch device (enabling passthrough in it) and the sink device * (enabling decompression in it). */ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, struct intel_connector *connector, const struct intel_crtc_state *new_crtc_state) { … } /** * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device * @state: atomic state * @connector: connector to disable the decompression for * @old_crtc_state: old state for the CRTC driving @connector * * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD * register of the appropriate sink/branch device, corresponding to the * sequence in intel_dp_sink_enable_decompression(). */ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, struct intel_connector *connector, const struct intel_crtc_state *old_crtc_state) { … } static void intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) { … } void intel_dp_wait_source_oui(struct intel_dp *intel_dp) { … } /* If the device supports it, try to set the power state appropriately */ void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) { … } static bool intel_dp_get_dpcd(struct intel_dp *intel_dp); /** * intel_dp_sync_state - sync the encoder state during init/resume * @encoder: intel encoder to sync * @crtc_state: state for the CRTC connected to the encoder * * Sync any state stored in the encoder wrt. HW state during driver init * and system resume. */ void intel_dp_sync_state(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { … } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { … } static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) { … } static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) { … } static int intel_dp_pcon_set_frl_mask(int max_frl) { … } static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) { … } static bool intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, u8 max_frl_bw_mask, u8 *frl_trained_mask) { … } static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) { … } static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) { … } static int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) { … } void intel_dp_check_frl_training(struct intel_dp *intel_dp) { … } static int intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) { … } static int intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static int intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int num_slices, int slice_width) { … } void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) { … } static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { … } void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) { … } static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) { … } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, struct drm_display_mode *mode) { … } void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) { … } static void intel_edp_mso_init(struct intel_dp *intel_dp) { … } static bool intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) { … } static bool intel_dp_has_sink_count(struct intel_dp *intel_dp) { … } void intel_dp_update_sink_caps(struct intel_dp *intel_dp) { … } static bool intel_dp_get_dpcd(struct intel_dp *intel_dp) { … } static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) { … } static enum drm_dp_mst_mode intel_dp_mst_mode_choose(struct intel_dp *intel_dp, enum drm_dp_mst_mode sink_mst_mode) { … } static enum drm_dp_mst_mode intel_dp_mst_detect(struct intel_dp *intel_dp) { … } static void intel_dp_mst_configure(struct intel_dp *intel_dp) { … } static void intel_dp_mst_disconnect(struct intel_dp *intel_dp) { … } static bool intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) { … } static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) { … } bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, struct dp_sdp *sdp, size_t size) { … } static ssize_t intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915, const struct hdmi_drm_infoframe *drm_infoframe, struct dp_sdp *sdp, size_t size) { … } static void intel_write_dp_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type) { … } void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { … } static int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, const void *buffer, size_t size) { … } static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, const void *buffer, size_t size) { … } static void intel_read_dp_as_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_dp_as_sdp *as_sdp) { … } static int intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, const void *buffer, size_t size) { … } static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc) { … } static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct hdmi_drm_infoframe *drm_infoframe) { … } void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type) { … } static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) { … } static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) { … } static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) { … } static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static void intel_dp_process_phy_request(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) { … } static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { … } static bool intel_dp_link_ok(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]) { … } static void intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) { … } static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) { … } /** * intel_dp_check_mst_status - service any pending MST interrupts, check link status * @intel_dp: Intel DP struct * * Read any pending MST interrupts, call MST core to handle these and ack the * interrupts. Check if the main and AUX link state is ok. * * Returns: * - %true if pending interrupts were serviced (or no interrupts were * pending) w/o detecting an error condition. * - %false if an error condition - like AUX failure or a loss of link - is * detected, or another condition - like a DP tunnel BW state change - needs * servicing from the hotplug work. */ static bool intel_dp_check_mst_status(struct intel_dp *intel_dp) { … } static void intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) { … } static bool intel_dp_needs_link_retrain(struct intel_dp *intel_dp) { … } static bool intel_dp_has_connector(struct intel_dp *intel_dp, const struct drm_connector_state *conn_state) { … } int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) { … } static bool intel_dp_is_connected(struct intel_dp *intel_dp) { … } static int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { … } void intel_dp_link_check(struct intel_encoder *encoder) { … } void intel_dp_check_link_state(struct intel_dp *intel_dp) { … } static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) { … } static int intel_dp_do_phy_test(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { … } void intel_dp_phy_test(struct intel_encoder *encoder) { … } static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) { … } static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) { … } /* * According to DP spec * 5.1.2: * 1. Read DPCD * 2. Configure link according to Receiver Capabilities * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 * 4. Check link status on receipt of hot-plug interrupt * * intel_dp_short_pulse - handles short pulse interrupts * when full detection is not required. * Returns %true if short pulse is handled and full detection * is NOT required and %false otherwise. */ static bool intel_dp_short_pulse(struct intel_dp *intel_dp) { … } /* XXX this is probably wrong for multiple downstream ports */ static enum drm_connector_status intel_dp_detect_dpcd(struct intel_dp *intel_dp) { … } static enum drm_connector_status edp_detect(struct intel_dp *intel_dp) { … } void intel_digital_port_lock(struct intel_encoder *encoder) { … } void intel_digital_port_unlock(struct intel_encoder *encoder) { … } /* * intel_digital_port_connected_locked - is the specified port connected? * @encoder: intel_encoder * * In cases where there's a connector physically connected but it can't be used * by our hardware we also return false, since the rest of the driver should * pretty much treat the port as disconnected. This is relevant for type-C * (starting on ICL) where there's ownership involved. * * The caller must hold the lock acquired by calling intel_digital_port_lock() * when calling this function. * * Return %true if port is connected, %false otherwise. */ bool intel_digital_port_connected_locked(struct intel_encoder *encoder) { … } bool intel_digital_port_connected(struct intel_encoder *encoder) { … } static const struct drm_edid * intel_dp_get_edid(struct intel_dp *intel_dp) { … } static void intel_dp_update_dfp(struct intel_dp *intel_dp, const struct drm_edid *drm_edid) { … } static bool intel_dp_can_ycbcr420(struct intel_dp *intel_dp) { … } static void intel_dp_update_420(struct intel_dp *intel_dp) { … } static void intel_dp_set_edid(struct intel_dp *intel_dp) { … } static void intel_dp_unset_edid(struct intel_dp *intel_dp) { … } static void intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) { … } static void intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) { … } static int intel_dp_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, bool force) { … } static void intel_dp_force(struct drm_connector *connector) { … } static int intel_dp_get_modes(struct drm_connector *connector) { … } static int intel_dp_connector_register(struct drm_connector *connector) { … } static void intel_dp_connector_unregister(struct drm_connector *connector) { … } void intel_dp_connector_sync_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state) { … } void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) { … } void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) { … } void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) { … } static int intel_modeset_tile_group(struct intel_atomic_state *state, int tile_group_id) { … } static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) { … } static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, struct drm_connector *connector) { … } static int intel_dp_connector_atomic_check(struct drm_connector *conn, struct drm_atomic_state *_state) { … } static void intel_dp_oob_hotplug_event(struct drm_connector *connector, enum drm_connector_status hpd_state) { … } static const struct drm_connector_funcs intel_dp_connector_funcs = …; static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = …; enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) { … } static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv, const struct intel_bios_encoder_data *devdata, enum port port) { … } bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port) { … } bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) { … } static void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) { … } static void intel_edp_add_properties(struct intel_dp *intel_dp) { … } static void intel_edp_backlight_setup(struct intel_dp *intel_dp, struct intel_connector *connector) { … } static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct intel_connector *intel_connector) { … } static void intel_dp_modeset_retry_work_fn(struct work_struct *work) { … } void intel_dp_init_modeset_retry_work(struct intel_connector *connector) { … } bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector) { … } void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) { … } void intel_dp_mst_resume(struct drm_i915_private *dev_priv) { … }
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