/* * Copyright © 2008-2015 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #include <drm/display/drm_dp_helper.h> #include "i915_drv.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_encoder.h" #include "intel_hotplug.h" #include "intel_panel.h" #define LT_MSG_PREFIX … #define LT_MSG_ARGS(_intel_dp, _dp_phy) … #define lt_dbg(_intel_dp, _dp_phy, _format, ...) … #define lt_err(_intel_dp, _dp_phy, _format, ...) … static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) { … } static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) { … } static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy) { … } static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } static bool intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) { … } static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) { … } /* * Read the LTTPR common capabilities and switch the LTTPR PHYs to * non-transparent mode if this is supported. Preserve the * transparent/non-transparent mode on an active link. * * Return the number of detected LTTPRs in non-transparent mode or 0 if the * LTTPRs are in transparent mode or the detection failed. */ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { … } /** * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode * @intel_dp: Intel DP struct * * Read the LTTPR common and DPRX capabilities and switch to non-transparent * link training mode if any is detected and read the PHY capabilities for all * detected LTTPRs. In case of an LTTPR detection error or if the number of * LTTPRs is more than is supported (8), fall back to the no-LTTPR, * transparent mode link training mode. * * Returns: * >0 if LTTPRs were detected and the non-transparent LT mode was set. The * DPRX capabilities are read out. * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a * detection failure and the transparent LT mode was set. The DPRX * capabilities are read out. * <0 Reading out the DPRX capabilities failed. */ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) { … } static u8 dp_voltage_max(u8 preemph) { … } static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static bool intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } /* 128b/132b */ static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } /* 8b/10b */ static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, const u8 link_status[DP_LINK_STATUS_SIZE], int lane) { … } #define TRAIN_REQ_FMT … #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) … #define TRAIN_REQ_VSWING_ARGS(link_status) … #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) … #define TRAIN_REQ_PREEMPH_ARGS(link_status) … #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) … #define TRAIN_REQ_TX_FFE_ARGS(link_status) … void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, const u8 link_status[DP_LINK_STATUS_SIZE]) { … } static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static bool intel_dp_set_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, u8 dp_train_pat) { … } static char dp_training_pattern_name(u8 train_pat) { … } void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, u8 dp_train_pat) { … } #define TRAIN_SET_FMT … #define _TRAIN_SET_VSWING_ARGS(train_set) … #define TRAIN_SET_VSWING_ARGS(train_set) … #define _TRAIN_SET_PREEMPH_ARGS(train_set) … #define TRAIN_SET_PREEMPH_ARGS(train_set) … #define _TRAIN_SET_TX_FFE_ARGS(train_set) … #define TRAIN_SET_TX_FFE_ARGS(train_set) … void intel_dp_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } static bool intel_dp_reset_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy, u8 dp_train_pat) { … } static bool intel_dp_update_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } /* 128b/132b */ static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) { … } /* * 8b/10b * * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to * have self contradicting tests around this area. * * In lieu of better ideas let's just stop when we've reached the max supported * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on * whether vswing level 3 is supported or not. */ static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) { … } static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) { … } static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, int link_bw, int rate_select, int lane_count, bool enhanced_framing) { … } static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, u8 link_bw, u8 rate_select) { … } /* * Prepare link training by configuring the link parameters. On DDI platforms * also enable the port here. */ static bool intel_dp_prepare_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, const u8 old_link_status[DP_LINK_STATUS_SIZE], const u8 new_link_status[DP_LINK_STATUS_SIZE]) { … } void intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, const u8 link_status[DP_LINK_STATUS_SIZE]) { … } /* * Perform the link training clock recovery phase on the given DP PHY using * training pattern 1. */ static bool intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } /* * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or * 1.2 devices that support it, TPS2 otherwise. */ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } /* * Perform the link training channel equalization phase on the given DP PHY * using one of training pattern 2, 3 or 4 depending on the source and * sink capabilities. */ static bool intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { … } static int intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } /** * intel_dp_stop_link_train - stop link training * @intel_dp: DP struct * @crtc_state: state for CRTC attached to the encoder * * Stop the link training of the @intel_dp port, disabling the training * pattern in the sink's DPCD, and disabling the test pattern symbol * generation on the port. * * What symbols are output on the port after this point is * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern * with the pipe being disabled, on older platforms it's HW specific if/how an * idle pattern is generated, as the pipe is already enabled here for those. * * This function must be called after intel_dp_start_link_train(). */ void intel_dp_stop_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static bool intel_dp_link_train_phy(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy) { … } static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, int link_rate, u8 lane_count) { … } static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int *new_link_rate, int *new_lane_count) { … } static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) { … } static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) { … } static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int *new_link_rate, int *new_lane_count) { … } static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int *new_link_rate, int *new_lane_count) { … } static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } /* Perform the link training on all LTTPRs and the DPRX on a link. */ static bool intel_dp_link_train_all_phys(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int lttpr_count) { … } /* * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) */ static bool intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } /* * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) */ static bool intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int lttpr_count) { … } /* * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) */ static bool intel_dp_128b132b_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int lttpr_count) { … } /** * intel_dp_start_link_train - start link training * @state: Atomic state * @intel_dp: DP struct * @crtc_state: state for CRTC attached to the encoder * * Start the link training of the @intel_dp port, scheduling a fallback * retraining with reduced link rate/lane parameters if the link training * fails. * After calling this function intel_dp_stop_link_train() must be called. */ void intel_dp_start_link_train(struct intel_atomic_state *state, struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { … } static struct intel_dp *intel_connector_to_intel_dp(struct intel_connector *connector) { … } static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) { … } static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) { … } static ssize_t i915_dp_force_link_rate_write(struct file *file, const char __user *ubuf, size_t len, loff_t *offp) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) { … } static int parse_lane_count(const char __user *ubuf, size_t len) { … } static ssize_t i915_dp_force_lane_count_write(struct file *file, const char __user *ubuf, size_t len, loff_t *offp) { … } DEFINE_SHOW_STORE_ATTRIBUTE(…); static int i915_dp_max_link_rate_show(void *data, u64 *val) { … } DEFINE_DEBUGFS_ATTRIBUTE(…); static int i915_dp_max_lane_count_show(void *data, u64 *val) { … } DEFINE_DEBUGFS_ATTRIBUTE(…); static int i915_dp_force_link_training_failure_show(void *data, u64 *val) { … } static int i915_dp_force_link_training_failure_write(void *data, u64 val) { … } DEFINE_DEBUGFS_ATTRIBUTE(…); static int i915_dp_force_link_retrain_show(void *data, u64 *val) { … } static int i915_dp_force_link_retrain_write(void *data, u64 val) { … } DEFINE_DEBUGFS_ATTRIBUTE(…); static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) { … } DEFINE_SHOW_ATTRIBUTE(…); void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { … }
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