/* * Copyright (c) 2006 Dave Airlie <[email protected]> * Copyright © 2006-2008,2010 Intel Corporation * Jesse Barnes <[email protected]> * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Eric Anholt <[email protected]> * Chris Wilson <[email protected]> */ #include <linux/export.h> #include <linux/i2c-algo-bit.h> #include <linux/i2c.h> #include <drm/display/drm_hdcp_helper.h> #include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_gmbus.h" #include "intel_gmbus_regs.h" struct intel_gmbus { … }; enum gmbus_gpio { … }; struct gmbus_pin { … }; /* Map gmbus pin pairs to names and registers. */ static const struct gmbus_pin gmbus_pins[] = …; static const struct gmbus_pin gmbus_pins_bdw[] = …; static const struct gmbus_pin gmbus_pins_skl[] = …; static const struct gmbus_pin gmbus_pins_bxt[] = …; static const struct gmbus_pin gmbus_pins_cnp[] = …; static const struct gmbus_pin gmbus_pins_icp[] = …; static const struct gmbus_pin gmbus_pins_dg1[] = …; static const struct gmbus_pin gmbus_pins_dg2[] = …; static const struct gmbus_pin gmbus_pins_mtp[] = …; static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, unsigned int pin) { … } bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) { … } /* Intel GPIO access functions */ #define I2C_RISEFALL_TIME … static inline struct intel_gmbus * to_intel_gmbus(struct i2c_adapter *i2c) { … } void intel_gmbus_reset(struct drm_i915_private *i915) { … } static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, bool enable) { … } static void pch_gmbus_clock_gating(struct drm_i915_private *i915, bool enable) { … } static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, bool enable) { … } static u32 get_reserved(struct intel_gmbus *bus) { … } static int get_clock(void *data) { … } static int get_data(void *data) { … } static void set_clock(void *data, int state_high) { … } static void set_data(void *data, int state_high) { … } static int intel_gpio_pre_xfer(struct i2c_adapter *adapter) { … } static void intel_gpio_post_xfer(struct i2c_adapter *adapter) { … } static void intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) { … } static bool has_gmbus_irq(struct drm_i915_private *i915) { … } static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) { … } static int gmbus_wait_idle(struct drm_i915_private *i915) { … } static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) { … } static int gmbus_xfer_read_chunk(struct drm_i915_private *i915, unsigned short addr, u8 *buf, unsigned int len, u32 gmbus0_reg, u32 gmbus1_index) { … } /* * HW spec says that 512Bytes in Burst read need special treatment. * But it doesn't talk about other multiple of 256Bytes. And couldn't locate * an I2C target, which supports such a lengthy burst read too for experiments. * * So until things get clarified on HW support, to avoid the burst read length * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. */ #define INTEL_GMBUS_BURST_READ_MAX_LEN … static int gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, u32 gmbus0_reg, u32 gmbus1_index) { … } static int gmbus_xfer_write_chunk(struct drm_i915_private *i915, unsigned short addr, u8 *buf, unsigned int len, u32 gmbus1_index) { … } static int gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, u32 gmbus1_index) { … } /* * The gmbus controller can combine a 1 or 2 byte write with another read/write * that immediately follows it by using an "INDEX" cycle. */ static bool gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) { … } static int gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, u32 gmbus0_reg) { … } static int do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, u32 gmbus0_source) { … } static int gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { … } int intel_gmbus_output_aksv(struct i2c_adapter *adapter) { … } static u32 gmbus_func(struct i2c_adapter *adapter) { … } static const struct i2c_algorithm gmbus_algorithm = …; static void gmbus_lock_bus(struct i2c_adapter *adapter, unsigned int flags) { … } static int gmbus_trylock_bus(struct i2c_adapter *adapter, unsigned int flags) { … } static void gmbus_unlock_bus(struct i2c_adapter *adapter, unsigned int flags) { … } static const struct i2c_lock_operations gmbus_lock_ops = …; /** * intel_gmbus_setup - instantiate all Intel i2c GMBuses * @i915: i915 device private */ int intel_gmbus_setup(struct drm_i915_private *i915) { … } struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, unsigned int pin) { … } void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) { … } bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) { … } void intel_gmbus_teardown(struct drm_i915_private *i915) { … } void intel_gmbus_irq_handler(struct drm_i915_private *i915) { … }
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