linux/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2022 Intel Corporation
 */

#ifndef __INTEL_SNPS_PHY_REGS__
#define __INTEL_SNPS_PHY_REGS__

#include "intel_display_reg_defs.h"

#define _SNPS_PHY_A_BASE …
#define _SNPS_PHY_B_BASE …
#define _SNPS_PHY(phy) …
#define _SNPS2(phy, reg) …
#define _MMIO_SNPS(phy, reg) …
#define _MMIO_SNPS_LN(ln, phy, reg) …

#define SNPS_PHY_MPLLB_CP(phy) …
#define SNPS_PHY_MPLLB_CP_INT …
#define SNPS_PHY_MPLLB_CP_INT_GS …
#define SNPS_PHY_MPLLB_CP_PROP …
#define SNPS_PHY_MPLLB_CP_PROP_GS …

#define SNPS_PHY_MPLLB_DIV(phy) …
#define SNPS_PHY_MPLLB_FORCE_EN …
#define SNPS_PHY_MPLLB_DIV_CLK_EN …
#define SNPS_PHY_MPLLB_DIV5_CLK_EN …
#define SNPS_PHY_MPLLB_V2I …
#define SNPS_PHY_MPLLB_FREQ_VCO …
#define SNPS_PHY_MPLLB_DIV_MULTIPLIER …
#define SNPS_PHY_MPLLB_PMIX_EN …
#define SNPS_PHY_MPLLB_DP2_MODE …
#define SNPS_PHY_MPLLB_WORD_DIV2_EN …
#define SNPS_PHY_MPLLB_TX_CLK_DIV …
#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL …

#define SNPS_PHY_MPLLB_FRACN1(phy) …
#define SNPS_PHY_MPLLB_FRACN_EN …
#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN …
#define SNPS_PHY_MPLLB_FRACN_DEN …

#define SNPS_PHY_MPLLB_FRACN2(phy) …
#define SNPS_PHY_MPLLB_FRACN_REM …
#define SNPS_PHY_MPLLB_FRACN_QUOT …

#define SNPS_PHY_MPLLB_SSCEN(phy) …
#define SNPS_PHY_MPLLB_SSC_EN …
#define SNPS_PHY_MPLLB_SSC_UP_SPREAD …
#define SNPS_PHY_MPLLB_SSC_PEAK …

#define SNPS_PHY_MPLLB_SSCSTEP(phy) …
#define SNPS_PHY_MPLLB_SSC_STEPSIZE …

#define SNPS_PHY_MPLLB_DIV2(phy) …
#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV …
#define SNPS_PHY_MPLLB_HDMI_DIV …
#define SNPS_PHY_MPLLB_REF_CLK_DIV …
#define SNPS_PHY_MPLLB_MULTIPLIER …

#define SNPS_PHY_REF_CONTROL(phy) …
#define SNPS_PHY_REF_CONTROL_REF_RANGE …

#define SNPS_PHY_TX_REQ(phy) …
#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR …

#define SNPS_PHY_TX_EQ(ln, phy) …
#define SNPS_PHY_TX_EQ_MAIN …
#define SNPS_PHY_TX_EQ_POST …
#define SNPS_PHY_TX_EQ_PRE …

#endif /* __INTEL_SNPS_PHY_REGS__ */