/* SPDX-License-Identifier: MIT */ /* * Copyright © 2022 Intel Corporation */ #ifndef __VLV_DSI_PLL_REGS_H__ #define __VLV_DSI_PLL_REGS_H__ #include "vlv_dsi_regs.h" #define MIPIO_TXESC_CLK_DIV1 … #define GLK_TX_ESC_CLK_DIV1_MASK … #define MIPIO_TXESC_CLK_DIV2 … #define GLK_TX_ESC_CLK_DIV2_MASK … #define BXT_MAX_VAR_OUTPUT_KHZ … #define BXT_MIPI_CLOCK_CTL … #define BXT_MIPI1_DIV_SHIFT … #define BXT_MIPI2_DIV_SHIFT … #define BXT_MIPI_DIV_SHIFT(port) … /* TX control divider to select actual TX clock output from (8x/var) */ #define BXT_MIPI1_TX_ESCLK_SHIFT … #define BXT_MIPI2_TX_ESCLK_SHIFT … #define BXT_MIPI_TX_ESCLK_SHIFT(port) … #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK … #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK … #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) … #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) … /* RX upper control divider to select actual RX clock output from 8x */ #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT … #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT … #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) … #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK … #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK … #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) … #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) … /* 8/3X divider to select the actual 8/3X clock output from 8x */ #define BXT_MIPI1_8X_BY3_SHIFT … #define BXT_MIPI2_8X_BY3_SHIFT … #define BXT_MIPI_8X_BY3_SHIFT(port) … #define BXT_MIPI1_8X_BY3_DIVIDER_MASK … #define BXT_MIPI2_8X_BY3_DIVIDER_MASK … #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) … #define BXT_MIPI_8X_BY3_DIVIDER(port, val) … /* RX lower control divider to select actual RX clock output from 8x */ #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT … #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT … #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) … #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK … #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK … #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) … #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) … #define RX_DIVIDER_BIT_1_2 … #define RX_DIVIDER_BIT_3_4 … #define BXT_DSI_PLL_CTL … #define BXT_DSI_PLL_PVD_RATIO_SHIFT … #define BXT_DSI_PLL_PVD_RATIO_MASK … #define BXT_DSI_PLL_PVD_RATIO_1 … #define BXT_DSIC_16X_BY1 … #define BXT_DSIC_16X_BY2 … #define BXT_DSIC_16X_BY3 … #define BXT_DSIC_16X_BY4 … #define BXT_DSIC_16X_MASK … #define BXT_DSIA_16X_BY1 … #define BXT_DSIA_16X_BY2 … #define BXT_DSIA_16X_BY3 … #define BXT_DSIA_16X_BY4 … #define BXT_DSIA_16X_MASK … #define BXT_DSI_FREQ_SEL_SHIFT … #define BXT_DSI_FREQ_SEL_MASK … #define BXT_DSI_PLL_RATIO_MAX … #define BXT_DSI_PLL_RATIO_MIN … #define GLK_DSI_PLL_RATIO_MAX … #define GLK_DSI_PLL_RATIO_MIN … #define BXT_DSI_PLL_RATIO_MASK … #define BXT_REF_CLOCK_KHZ … #define BXT_DSI_PLL_ENABLE … #define BXT_DSI_PLL_DO_ENABLE … #define BXT_DSI_PLL_LOCKED … #endif /* __VLV_DSI_PLL_REGS_H__ */
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