linux/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020 Nuvoton Technology corporation.

#include <linux/bits.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/mod_devicetable.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>

/* GCR registers */
#define NPCM8XX_GCR_SRCNT
#define NPCM8XX_GCR_FLOCKR1
#define NPCM8XX_GCR_DSCNT
#define NPCM8XX_GCR_I2CSEGSEL
#define NPCM8XX_GCR_MFSEL1
#define NPCM8XX_GCR_MFSEL2
#define NPCM8XX_GCR_MFSEL3
#define NPCM8XX_GCR_MFSEL4
#define NPCM8XX_GCR_MFSEL5
#define NPCM8XX_GCR_MFSEL6
#define NPCM8XX_GCR_MFSEL7

#define SRCNT_ESPI

/* GPIO registers */
#define NPCM8XX_GP_N_TLOCK1
#define NPCM8XX_GP_N_DIN
#define NPCM8XX_GP_N_POL
#define NPCM8XX_GP_N_DOUT
#define NPCM8XX_GP_N_OE
#define NPCM8XX_GP_N_OTYP
#define NPCM8XX_GP_N_MP
#define NPCM8XX_GP_N_PU
#define NPCM8XX_GP_N_PD
#define NPCM8XX_GP_N_DBNC
#define NPCM8XX_GP_N_EVTYP
#define NPCM8XX_GP_N_EVBE
#define NPCM8XX_GP_N_OBL0
#define NPCM8XX_GP_N_OBL1
#define NPCM8XX_GP_N_OBL2
#define NPCM8XX_GP_N_OBL3
#define NPCM8XX_GP_N_EVEN
#define NPCM8XX_GP_N_EVENS
#define NPCM8XX_GP_N_EVENC
#define NPCM8XX_GP_N_EVST
#define NPCM8XX_GP_N_SPLCK
#define NPCM8XX_GP_N_MPLCK
#define NPCM8XX_GP_N_IEM
#define NPCM8XX_GP_N_OSRC
#define NPCM8XX_GP_N_ODSC
#define NPCM8XX_GP_N_DOS
#define NPCM8XX_GP_N_DOC
#define NPCM8XX_GP_N_OES
#define NPCM8XX_GP_N_OEC
#define NPCM8XX_GP_N_DBNCS0
#define NPCM8XX_GP_N_DBNCS1
#define NPCM8XX_GP_N_DBNCP0
#define NPCM8XX_GP_N_DBNCP1
#define NPCM8XX_GP_N_DBNCP2
#define NPCM8XX_GP_N_DBNCP3
#define NPCM8XX_GP_N_TLOCK2

#define NPCM8XX_GPIO_PER_BANK
#define NPCM8XX_GPIO_BANK_NUM
#define NPCM8XX_GCR_NONE

#define NPCM8XX_DEBOUNCE_MAX
#define NPCM8XX_DEBOUNCE_NSEC
#define NPCM8XX_DEBOUNCE_VAL_MASK
#define NPCM8XX_DEBOUNCE_MAX_VAL

/* Structure for register banks */
struct debounce_time {};

struct npcm8xx_gpio {};

struct npcm8xx_pinctrl {};

/* GPIO handling in the pinctrl driver */
static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
			  unsigned int pinmask)
{}

static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
			  unsigned int pinmask)
{}

static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{}

static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{}

static int npcmgpio_direction_output(struct gpio_chip *chip,
				     unsigned int offset, int value)
{}

static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
{}

static void npcmgpio_irq_handler(struct irq_desc *desc)
{}

static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
{}

static void npcmgpio_irq_ack(struct irq_data *d)
{}

static void npcmgpio_irq_mask(struct irq_data *d)
{}

static void npcmgpio_irq_unmask(struct irq_data *d)
{}

static unsigned int npcmgpio_irq_startup(struct irq_data *d)
{}

static struct irq_chip npcmgpio_irqchip =;

static const int gpi36_pins[] =;
static const int gpi35_pins[] =;

static const int tp_jtag3_pins[] =;
static const int tp_uart_pins[] =;

static const int tp_smb2_pins[] =;
static const int tp_smb1_pins[] =;

static const int tp_gpio7_pins[] =;
static const int tp_gpio6_pins[] =;
static const int tp_gpio5_pins[] =;
static const int tp_gpio4_pins[] =;
static const int tp_gpio3_pins[] =;
static const int tp_gpio2_pins[] =;
static const int tp_gpio1_pins[] =;
static const int tp_gpio0_pins[] =;

static const int tp_gpio2b_pins[] =;
static const int tp_gpio1b_pins[] =;
static const int tp_gpio0b_pins[] =;

static const int vgadig_pins[] =;

static const int nbu1crts_pins[] =;

static const int fm2_pins[] =;
static const int fm1_pins[] =;
static const int fm0_pins[] =;

static const int gpio1836_pins[] =;
static const int gpio1889_pins[] =;
static const int gpo187_pins[] =;

static const int cp1urxd_pins[] =;
static const int r3rxer_pins[] =;

static const int cp1gpio2c_pins[] =;
static const int cp1gpio3c_pins[] =;

static const int cp1gpio0b_pins[] =;
static const int cp1gpio1b_pins[] =;
static const int cp1gpio2b_pins[] =;
static const int cp1gpio3b_pins[] =;
static const int cp1gpio4b_pins[] =;
static const int cp1gpio5b_pins[] =;
static const int cp1gpio6b_pins[] =;
static const int cp1gpio7b_pins[] =;

static const int cp1gpio0_pins[] =;
static const int cp1gpio1_pins[] =;
static const int cp1gpio2_pins[] =;
static const int cp1gpio3_pins[] =;
static const int cp1gpio4_pins[] =;
static const int cp1gpio5_pins[] =;
static const int cp1gpio6_pins[] =;
static const int cp1gpio7_pins[] =;

static const int cp1utxd_pins[] =;

static const int spi1cs3_pins[] =;
static const int spi1cs2_pins[] =;
static const int spi1cs1_pins[] =;
static const int spi1cs0_pins[] =;

static const int spi1d23_pins[] =;

static const int j2j3_pins[] =;

static const int r3oen_pins[] =;
static const int r2oen_pins[] =;
static const int r1oen_pins[] =;
static const int bu4b_pins[] =;
static const int bu4_pins[] =;
static const int bu5b_pins[] =;
static const int bu5_pins[] =;
static const int bu6_pins[] =;
static const int rmii3_pins[] =;

static const int jm1_pins[] =;
static const int jm2_pins[] =;

static const int tpgpio5b_pins[] =;
static const int tpgpio4b_pins[] =;

static const int clkrun_pins[] =;

static const int i3c5_pins[] =;
static const int i3c4_pins[] =;
static const int i3c3_pins[] =;
static const int i3c2_pins[] =;
static const int i3c1_pins[] =;
static const int i3c0_pins[] =;

static const int hsi1a_pins[] =;
static const int hsi2a_pins[] =;
static const int hsi1b_pins[] =;
static const int hsi2b_pins[] =;
static const int hsi1c_pins[] =;
static const int hsi2c_pins[] =;

static const int smb0_pins[]  =;
static const int smb0b_pins[] =;
static const int smb0c_pins[] =;
static const int smb0d_pins[] =;
static const int smb0den_pins[] =;
static const int smb1_pins[]  =;
static const int smb1b_pins[] =;
static const int smb1c_pins[] =;
static const int smb1d_pins[] =;
static const int smb2_pins[]  =;
static const int smb2b_pins[] =;
static const int smb2c_pins[] =;
static const int smb2d_pins[] =;
static const int smb3_pins[]  =;
static const int smb3b_pins[] =;
static const int smb3c_pins[] =;
static const int smb3d_pins[] =;
static const int smb4_pins[]  =;
static const int smb4b_pins[] =;
static const int smb4c_pins[] =;
static const int smb4d_pins[] =;
static const int smb5_pins[]  =;
static const int smb5b_pins[] =;
static const int smb5c_pins[] =;
static const int smb5d_pins[] =;
static const int ga20kbc_pins[] =;

static const int smb6_pins[]  =;
static const int smb6b_pins[] =;
static const int smb6c_pins[]  =;
static const int smb6d_pins[]  =;
static const int smb7_pins[]  =;
static const int smb7b_pins[]  =;
static const int smb7c_pins[]  =;
static const int smb7d_pins[]  =;
static const int smb8_pins[]  =;
static const int smb9_pins[]  =;
static const int smb10_pins[] =;
static const int smb11_pins[] =;
static const int smb12_pins[] =;
static const int smb13_pins[] =;
static const int smb14_pins[] =;
static const int smb14b_pins[] =;
static const int smb15_pins[] =;
static const int smb15b_pins[] =;

static const int smb16_pins[] =;
static const int smb16b_pins[] =;
static const int smb17_pins[] =;
static const int smb18_pins[] =;
static const int smb19_pins[] =;
static const int smb20_pins[] =;
static const int smb21_pins[] =;
static const int smb22_pins[] =;
static const int smb23_pins[] =;
static const int smb23b_pins[] =;

static const int fanin0_pins[] =;
static const int fanin1_pins[] =;
static const int fanin2_pins[] =;
static const int fanin3_pins[] =;
static const int fanin4_pins[] =;
static const int fanin5_pins[] =;
static const int fanin6_pins[] =;
static const int fanin7_pins[] =;
static const int fanin8_pins[] =;
static const int fanin9_pins[] =;
static const int fanin10_pins[] =;
static const int fanin11_pins[] =;
static const int fanin12_pins[] =;
static const int fanin13_pins[] =;
static const int fanin14_pins[] =;
static const int fanin15_pins[] =;
static const int faninx_pins[] =;

static const int pwm0_pins[] =;
static const int pwm1_pins[] =;
static const int pwm2_pins[] =;
static const int pwm3_pins[] =;
static const int pwm4_pins[] =;
static const int pwm5_pins[] =;
static const int pwm6_pins[] =;
static const int pwm7_pins[] =;
static const int pwm8_pins[] =;
static const int pwm9_pins[] =;
static const int pwm10_pins[] =;
static const int pwm11_pins[] =;

static const int uart1_pins[] =;
static const int uart2_pins[] =;

static const int sg1mdio_pins[] =;

static const int rg2_pins[] =;
static const int rg2mdio_pins[] =;

static const int ddr_pins[] =;

static const int iox1_pins[] =;
static const int iox2_pins[] =;
static const int ioxh_pins[] =;

static const int mmc_pins[] =;
static const int mmcwp_pins[] =;
static const int mmccd_pins[] =;
static const int mmcrst_pins[] =;
static const int mmc8_pins[] =;

static const int r1_pins[] =;
static const int r1err_pins[] =;
static const int r1md_pins[] =;
static const int r2_pins[] =;
static const int r2err_pins[] =;
static const int r2md_pins[] =;
static const int sd1_pins[] =;
static const int sd1pwr_pins[] =;

static const int wdog1_pins[] =;
static const int wdog2_pins[] =;

static const int bmcuart0a_pins[] =;
static const int bmcuart0b_pins[] =;
static const int bmcuart1_pins[] =;

static const int scipme_pins[] =;
static const int smi_pins[] =;
static const int serirq_pins[] =;

static const int clkout_pins[] =;
static const int clkreq_pins[] =;

static const int jtag2_pins[] =;
static const int gspi_pins[] =;

static const int spix_pins[] =;
static const int spixcs1_pins[] =;

static const int spi1_pins[] =;
static const int pspi_pins[] =;

static const int spi0cs1_pins[] =;

static const int spi3_pins[] =;
static const int spi3cs1_pins[] =;
static const int spi3quad_pins[] =;
static const int spi3cs2_pins[] =;
static const int spi3cs3_pins[] =;

static const int ddc_pins[] =;

static const int lpc_pins[] =;
static const int espi_pins[] =;

static const int lkgpo0_pins[] =;
static const int lkgpo1_pins[] =;
static const int lkgpo2_pins[] =;

static const int nprd_smi_pins[] =;

static const int hgpio0_pins[] =;
static const int hgpio1_pins[] =;
static const int hgpio2_pins[] =;
static const int hgpio3_pins[] =;
static const int hgpio4_pins[] =;
static const int hgpio5_pins[] =;
static const int hgpio6_pins[] =;
static const int hgpio7_pins[] =;

/*
 * pin:	     name, number
 * group:    name, npins,   pins
 * function: name, ngroups, groups
 */
struct npcm8xx_pingroup {};

#define NPCM8XX_GRPS \
	\

enum {};

static struct npcm8xx_pingroup npcm8xx_pingroups[] =;

#define NPCM8XX_SFUNC(a)
#define NPCM8XX_FUNC(a, b...)
#define NPCM8XX_MKFUNC(nm)
struct npcm8xx_func {};

NPCM8XX_SFUNC(gpi36);
NPCM8XX_SFUNC(gpi35);
NPCM8XX_SFUNC(tp_jtag3);
NPCM8XX_SFUNC(tp_uart);
NPCM8XX_SFUNC(tp_smb2);
NPCM8XX_SFUNC(tp_smb1);
NPCM8XX_SFUNC(tp_gpio7);
NPCM8XX_SFUNC(tp_gpio6);
NPCM8XX_SFUNC(tp_gpio5);
NPCM8XX_SFUNC(tp_gpio4);
NPCM8XX_SFUNC(tp_gpio3);
NPCM8XX_SFUNC(tp_gpio2);
NPCM8XX_SFUNC(tp_gpio1);
NPCM8XX_SFUNC(tp_gpio0);
NPCM8XX_SFUNC(tp_gpio2b);
NPCM8XX_SFUNC(tp_gpio1b);
NPCM8XX_SFUNC(tp_gpio0b);
NPCM8XX_SFUNC(vgadig);
NPCM8XX_SFUNC(nbu1crts);
NPCM8XX_SFUNC(fm2);
NPCM8XX_SFUNC(fm1);
NPCM8XX_SFUNC(fm0);
NPCM8XX_SFUNC(gpio1836);
NPCM8XX_SFUNC(gpio1889);
NPCM8XX_SFUNC(gpo187);
NPCM8XX_SFUNC(cp1urxd);
NPCM8XX_SFUNC(r3rxer);
NPCM8XX_SFUNC(cp1gpio2c);
NPCM8XX_SFUNC(cp1gpio3c);
NPCM8XX_SFUNC(cp1gpio0b);
NPCM8XX_SFUNC(cp1gpio1b);
NPCM8XX_SFUNC(cp1gpio2b);
NPCM8XX_SFUNC(cp1gpio3b);
NPCM8XX_SFUNC(cp1gpio4b);
NPCM8XX_SFUNC(cp1gpio5b);
NPCM8XX_SFUNC(cp1gpio6b);
NPCM8XX_SFUNC(cp1gpio7b);
NPCM8XX_SFUNC(cp1gpio0);
NPCM8XX_SFUNC(cp1gpio1);
NPCM8XX_SFUNC(cp1gpio2);
NPCM8XX_SFUNC(cp1gpio3);
NPCM8XX_SFUNC(cp1gpio4);
NPCM8XX_SFUNC(cp1gpio5);
NPCM8XX_SFUNC(cp1gpio6);
NPCM8XX_SFUNC(cp1gpio7);
NPCM8XX_SFUNC(cp1utxd);
NPCM8XX_SFUNC(spi1cs3);
NPCM8XX_SFUNC(spi1cs2);
NPCM8XX_SFUNC(spi1cs1);
NPCM8XX_SFUNC(spi1cs0);
NPCM8XX_SFUNC(spi1d23);
NPCM8XX_SFUNC(j2j3);
NPCM8XX_SFUNC(r3oen);
NPCM8XX_SFUNC(r2oen);
NPCM8XX_SFUNC(r1oen);
NPCM8XX_SFUNC(bu4b);
NPCM8XX_SFUNC(bu4);
NPCM8XX_SFUNC(bu5b);
NPCM8XX_SFUNC(bu5);
NPCM8XX_SFUNC(bu6);
NPCM8XX_SFUNC(rmii3);
NPCM8XX_SFUNC(jm1);
NPCM8XX_SFUNC(jm2);
NPCM8XX_SFUNC(tpgpio5b);
NPCM8XX_SFUNC(tpgpio4b);
NPCM8XX_SFUNC(clkrun);
NPCM8XX_SFUNC(i3c5);
NPCM8XX_SFUNC(i3c4);
NPCM8XX_SFUNC(i3c3);
NPCM8XX_SFUNC(i3c2);
NPCM8XX_SFUNC(i3c1);
NPCM8XX_SFUNC(i3c0);
NPCM8XX_SFUNC(hsi1a);
NPCM8XX_SFUNC(hsi2a);
NPCM8XX_SFUNC(hsi1b);
NPCM8XX_SFUNC(hsi2b);
NPCM8XX_SFUNC(hsi1c);
NPCM8XX_SFUNC(hsi2c);
NPCM8XX_SFUNC(smb0);
NPCM8XX_SFUNC(smb0b);
NPCM8XX_SFUNC(smb0c);
NPCM8XX_SFUNC(smb0d);
NPCM8XX_SFUNC(smb0den);
NPCM8XX_SFUNC(smb1);
NPCM8XX_SFUNC(smb1b);
NPCM8XX_SFUNC(smb1c);
NPCM8XX_SFUNC(smb1d);
NPCM8XX_SFUNC(smb2);
NPCM8XX_SFUNC(smb2b);
NPCM8XX_SFUNC(smb2c);
NPCM8XX_SFUNC(smb2d);
NPCM8XX_SFUNC(smb3);
NPCM8XX_SFUNC(smb3b);
NPCM8XX_SFUNC(smb3c);
NPCM8XX_SFUNC(smb3d);
NPCM8XX_SFUNC(smb4);
NPCM8XX_SFUNC(smb4b);
NPCM8XX_SFUNC(smb4c);
NPCM8XX_SFUNC(smb4d);
NPCM8XX_SFUNC(smb5);
NPCM8XX_SFUNC(smb5b);
NPCM8XX_SFUNC(smb5c);
NPCM8XX_SFUNC(smb5d);
NPCM8XX_SFUNC(ga20kbc);
NPCM8XX_SFUNC(smb6);
NPCM8XX_SFUNC(smb6b);
NPCM8XX_SFUNC(smb6c);
NPCM8XX_SFUNC(smb6d);
NPCM8XX_SFUNC(smb7);
NPCM8XX_SFUNC(smb7b);
NPCM8XX_SFUNC(smb7c);
NPCM8XX_SFUNC(smb7d);
NPCM8XX_SFUNC(smb8);
NPCM8XX_SFUNC(smb9);
NPCM8XX_SFUNC(smb10);
NPCM8XX_SFUNC(smb11);
NPCM8XX_SFUNC(smb12);
NPCM8XX_SFUNC(smb13);
NPCM8XX_SFUNC(smb14);
NPCM8XX_SFUNC(smb14b);
NPCM8XX_SFUNC(smb15);
NPCM8XX_SFUNC(smb16);
NPCM8XX_SFUNC(smb16b);
NPCM8XX_SFUNC(smb17);
NPCM8XX_SFUNC(smb18);
NPCM8XX_SFUNC(smb19);
NPCM8XX_SFUNC(smb20);
NPCM8XX_SFUNC(smb21);
NPCM8XX_SFUNC(smb22);
NPCM8XX_SFUNC(smb23);
NPCM8XX_SFUNC(smb23b);
NPCM8XX_SFUNC(fanin0);
NPCM8XX_SFUNC(fanin1);
NPCM8XX_SFUNC(fanin2);
NPCM8XX_SFUNC(fanin3);
NPCM8XX_SFUNC(fanin4);
NPCM8XX_SFUNC(fanin5);
NPCM8XX_SFUNC(fanin6);
NPCM8XX_SFUNC(fanin7);
NPCM8XX_SFUNC(fanin8);
NPCM8XX_SFUNC(fanin9);
NPCM8XX_SFUNC(fanin10);
NPCM8XX_SFUNC(fanin11);
NPCM8XX_SFUNC(fanin12);
NPCM8XX_SFUNC(fanin13);
NPCM8XX_SFUNC(fanin14);
NPCM8XX_SFUNC(fanin15);
NPCM8XX_SFUNC(faninx);
NPCM8XX_SFUNC(pwm0);
NPCM8XX_SFUNC(pwm1);
NPCM8XX_SFUNC(pwm2);
NPCM8XX_SFUNC(pwm3);
NPCM8XX_SFUNC(pwm4);
NPCM8XX_SFUNC(pwm5);
NPCM8XX_SFUNC(pwm6);
NPCM8XX_SFUNC(pwm7);
NPCM8XX_SFUNC(pwm8);
NPCM8XX_SFUNC(pwm9);
NPCM8XX_SFUNC(pwm10);
NPCM8XX_SFUNC(pwm11);
NPCM8XX_SFUNC(sg1mdio);
NPCM8XX_SFUNC(rg2);
NPCM8XX_SFUNC(rg2mdio);
NPCM8XX_SFUNC(ddr);
NPCM8XX_SFUNC(uart1);
NPCM8XX_SFUNC(uart2);
NPCM8XX_SFUNC(bmcuart0a);
NPCM8XX_SFUNC(bmcuart0b);
NPCM8XX_SFUNC(bmcuart1);
NPCM8XX_SFUNC(iox1);
NPCM8XX_SFUNC(iox2);
NPCM8XX_SFUNC(ioxh);
NPCM8XX_SFUNC(gspi);
NPCM8XX_SFUNC(mmc);
NPCM8XX_SFUNC(mmcwp);
NPCM8XX_SFUNC(mmccd);
NPCM8XX_SFUNC(mmcrst);
NPCM8XX_SFUNC(mmc8);
NPCM8XX_SFUNC(r1);
NPCM8XX_SFUNC(r1err);
NPCM8XX_SFUNC(r1md);
NPCM8XX_SFUNC(r2);
NPCM8XX_SFUNC(r2err);
NPCM8XX_SFUNC(r2md);
NPCM8XX_SFUNC(sd1);
NPCM8XX_SFUNC(sd1pwr);
NPCM8XX_SFUNC(wdog1);
NPCM8XX_SFUNC(wdog2);
NPCM8XX_SFUNC(scipme);
NPCM8XX_SFUNC(smi);
NPCM8XX_SFUNC(serirq);
NPCM8XX_SFUNC(jtag2);
NPCM8XX_SFUNC(spix);
NPCM8XX_SFUNC(spixcs1);
NPCM8XX_SFUNC(spi1);
NPCM8XX_SFUNC(pspi);
NPCM8XX_SFUNC(ddc);
NPCM8XX_SFUNC(clkreq);
NPCM8XX_SFUNC(clkout);
NPCM8XX_SFUNC(spi3);
NPCM8XX_SFUNC(spi3cs1);
NPCM8XX_SFUNC(spi3quad);
NPCM8XX_SFUNC(spi3cs2);
NPCM8XX_SFUNC(spi3cs3);
NPCM8XX_SFUNC(spi0cs1);
NPCM8XX_SFUNC(lpc);
NPCM8XX_SFUNC(espi);
NPCM8XX_SFUNC(lkgpo0);
NPCM8XX_SFUNC(lkgpo1);
NPCM8XX_SFUNC(lkgpo2);
NPCM8XX_SFUNC(nprd_smi);
NPCM8XX_SFUNC(hgpio0);
NPCM8XX_SFUNC(hgpio1);
NPCM8XX_SFUNC(hgpio2);
NPCM8XX_SFUNC(hgpio3);
NPCM8XX_SFUNC(hgpio4);
NPCM8XX_SFUNC(hgpio5);
NPCM8XX_SFUNC(hgpio6);
NPCM8XX_SFUNC(hgpio7);

/* Function names */
static struct npcm8xx_func npcm8xx_funcs[] =;

#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q)

/* Drive strength controlled by NPCM8XX_GP_N_ODSC */
#define DRIVE_STRENGTH_LO_SHIFT
#define DRIVE_STRENGTH_HI_SHIFT
#define DRIVE_STRENGTH_MASK

#define DSTR(lo, hi)
#define DSLO(x)
#define DSHI(x)

#define GPI
#define GPO
#define SLEW
#define SLEWLPC

struct npcm8xx_pincfg {};

static const struct npcm8xx_pincfg pincfg[] =;

/* number, name, drv_data */
static const struct pinctrl_pin_desc npcm8xx_pins[] =;

/* Enable mode in pin group */
static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
			    int pin_number, int mode)
{}

static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
				 struct regmap *gcr_regmap, unsigned int pin)
{}

static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
				 struct regmap *gcr_regmap, unsigned int pin,
				 int arg)
{}

static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
				      unsigned int pin)
{}

static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm,
				      unsigned int pin, int nval)
{}

/* pinctrl_ops */
static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev)
{}

static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev,
					  unsigned int selector)
{}

static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const unsigned int **pins,
				  unsigned int *npins)
{}

static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev,
				  struct device_node *np_config,
				  struct pinctrl_map **map,
				  u32 *num_maps)
{}

static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev,
				struct pinctrl_map *map, u32 num_maps)
{}

static const struct pinctrl_ops npcm8xx_pinctrl_ops =;

static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev)
{}

static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev,
					     unsigned int function)
{}

static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev,
				       unsigned int function,
				       const char * const **groups,
				       unsigned int * const ngroups)
{}

static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
				  unsigned int function,
				  unsigned int group)
{}

static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
				       struct pinctrl_gpio_range *range,
				       unsigned int offset)
{}

static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned int offset)
{}

static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
				   struct pinctrl_gpio_range *range,
				   unsigned int offset, bool input)
{}

static const struct pinmux_ops npcm8xx_pinmux_ops =;

static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
				   u32 nanosecs)
{}

static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin,
			     u32 nanosecs)
{}

/* pinconf_ops */
static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
			      unsigned long *config)
{}

static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm,
				  unsigned int pin, unsigned long config)
{}

static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
			      unsigned long *configs, unsigned int num_configs)
{}

static const struct pinconf_ops npcm8xx_pinconf_ops =;

/* pinctrl_desc */
static struct pinctrl_desc npcm8xx_pinctrl_desc =;

static int npcmgpio_add_pin_ranges(struct gpio_chip *chip)
{}

static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
{}

static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
{}

static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
{}

static const struct of_device_id npcm8xx_pinctrl_match[] =;
MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match);

static struct platform_driver npcm8xx_pinctrl_driver =;

static int __init npcm8xx_pinctrl_register(void)
{}
arch_initcall(npcm8xx_pinctrl_register);

MODULE_LICENSE();
MODULE_AUTHOR();
MODULE_DESCRIPTION();