linux/drivers/gpu/drm/i915/display/intel_snps_phy.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2019 Intel Corporation
 */

#include <linux/math.h>

#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_snps_phy.h"
#include "intel_snps_phy_regs.h"

/**
 * DOC: Synopsis PHY support
 *
 * Synopsis PHYs are primarily programmed by looking up magic register values
 * in tables rather than calculating the necessary values at runtime.
 *
 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
 * an "MPLLB."  The MPLLB replaces the shared DPLL functionality used on other
 * platforms and must be programming directly during the modeset sequence
 * since it is not handled by the shared DPLL framework as on other platforms.
 */

void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
{ … }

void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
					   bool enable)
{ … }

void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
				      const struct intel_crtc_state *crtc_state)
{ … }

/*
 * Basic DP link rates with 100 MHz reference clock.
 */

static const struct intel_mpllb_state dg2_dp_rbr_100 = …;

static const struct intel_mpllb_state dg2_dp_hbr1_100 = …;

static const struct intel_mpllb_state dg2_dp_hbr2_100 = …;

static const struct intel_mpllb_state dg2_dp_hbr3_100 = …;

static const struct intel_mpllb_state dg2_dp_uhbr10_100 = …;

static const struct intel_mpllb_state dg2_dp_uhbr13_100 = …;

static const struct intel_mpllb_state * const dg2_dp_100_tables[] = …;

/*
 * eDP link rates with 100 MHz reference clock.
 */

static const struct intel_mpllb_state dg2_edp_r216 = …;

static const struct intel_mpllb_state dg2_edp_r243 = …;

static const struct intel_mpllb_state dg2_edp_r324 = …;

static const struct intel_mpllb_state dg2_edp_r432 = …;

static const struct intel_mpllb_state * const dg2_edp_tables[] = …;

/*
 * HDMI link rates with 100 MHz reference clock.
 */

static const struct intel_mpllb_state dg2_hdmi_25_175 = …;

static const struct intel_mpllb_state dg2_hdmi_27_0 = …;

static const struct intel_mpllb_state dg2_hdmi_74_25 = …;

static const struct intel_mpllb_state dg2_hdmi_148_5 = …;

/* values in the below table are calculted using the algo */
static const struct intel_mpllb_state dg2_hdmi_25200 = …;

static const struct intel_mpllb_state dg2_hdmi_27027 = …;

static const struct intel_mpllb_state dg2_hdmi_28320 = …;

static const struct intel_mpllb_state dg2_hdmi_30240 = …;

static const struct intel_mpllb_state dg2_hdmi_31500 = …;

static const struct intel_mpllb_state dg2_hdmi_36000 = …;

static const struct intel_mpllb_state dg2_hdmi_40000 = …;

static const struct intel_mpllb_state dg2_hdmi_49500 = …;

static const struct intel_mpllb_state dg2_hdmi_50000 = …;

static const struct intel_mpllb_state dg2_hdmi_57284 = …;

static const struct intel_mpllb_state dg2_hdmi_58000 = …;

static const struct intel_mpllb_state dg2_hdmi_65000 = …;

static const struct intel_mpllb_state dg2_hdmi_71000 = …;

static const struct intel_mpllb_state dg2_hdmi_74176 = …;

static const struct intel_mpllb_state dg2_hdmi_75000 = …;

static const struct intel_mpllb_state dg2_hdmi_78750 = …;

static const struct intel_mpllb_state dg2_hdmi_85500 = …;

static const struct intel_mpllb_state dg2_hdmi_88750 = …;

static const struct intel_mpllb_state dg2_hdmi_106500 = …;

static const struct intel_mpllb_state dg2_hdmi_108000 = …;

static const struct intel_mpllb_state dg2_hdmi_115500 = …;

static const struct intel_mpllb_state dg2_hdmi_119000 = …;

static const struct intel_mpllb_state dg2_hdmi_135000 = …;

static const struct intel_mpllb_state dg2_hdmi_138500 = …;

static const struct intel_mpllb_state dg2_hdmi_147160 = …;

static const struct intel_mpllb_state dg2_hdmi_148352 = …;

static const struct intel_mpllb_state dg2_hdmi_154000 = …;

static const struct intel_mpllb_state dg2_hdmi_162000 = …;

static const struct intel_mpllb_state dg2_hdmi_209800 = …;

static const struct intel_mpllb_state dg2_hdmi_262750 = …;

static const struct intel_mpllb_state dg2_hdmi_267300 = …;

static const struct intel_mpllb_state dg2_hdmi_268500 = …;

static const struct intel_mpllb_state dg2_hdmi_296703 = …;

static const struct intel_mpllb_state dg2_hdmi_241500 = …;

static const struct intel_mpllb_state dg2_hdmi_319890 = …;

static const struct intel_mpllb_state dg2_hdmi_497750 = …;

static const struct intel_mpllb_state dg2_hdmi_592000 = …;

static const struct intel_mpllb_state dg2_hdmi_593407 = …;

static const struct intel_mpllb_state dg2_hdmi_297 = …;

static const struct intel_mpllb_state dg2_hdmi_594 = …;

static const struct intel_mpllb_state * const dg2_hdmi_tables[] = …;

static const struct intel_mpllb_state * const *
intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
		       struct intel_encoder *encoder)
{ … }

int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
			   struct intel_encoder *encoder)
{ … }

void intel_mpllb_enable(struct intel_encoder *encoder,
			const struct intel_crtc_state *crtc_state)
{ … }

void intel_mpllb_disable(struct intel_encoder *encoder)
{ … }

int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
				const struct intel_mpllb_state *pll_state)
{ … }

void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
				  struct intel_mpllb_state *pll_state)
{ … }

int intel_snps_phy_check_hdmi_link_rate(int clock)
{ … }

void intel_mpllb_state_verify(struct intel_atomic_state *state,
			      struct intel_crtc *crtc)
{ … }